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? 2003 microchip technology inc. ds30235j pic16c62x data sheet eprom-based 8-bit cmos microcontrollers downloaded from: http:///
ds30235j - page ii ? 2003 microchip technology inc. information contained in this publication regarding de vice applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility t o ensure that your application meets with your specifications. no representation or warranty is given and no liability is a ssumed by microchip technology incorporated with respect to the accura cy or use of such information, or infringement of patents or other intellectual property rights arising from such use or othe rwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technol ogy incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registe red trademarks of microchip technology incorporated in the u.s .a. accuron, application maestro, dspic, dspicdem, dspicdem.net, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, sele ct mode, smartsensor, smartshunt, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s .a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2003, microchip technology incorporated, printed in th e u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection f eature on microchip devices: microchip products meet the specification contained in the ir particular microchip data sheet. microchip believes that its family of products is one of t he most secure families of its kind on the market today, w hen used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these method s, to our knowledge, require using the microchip products in a man ner outside the operating specifications contained in micr ochip's data sheets. most likely, the person doing so is engaged in th eft of intellectual property. microchip is willing to work with the customer who is conce rned about the integrity of their code. neither microchip nor any other semiconductor manufacture r can guarantee the security of their code. code protecti on does not mean that we are guaranteeing the product as ?unbreaka ble.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection fe atures of our products. attempts to break microchip?s code protection fe ature may be a violation of the digital millennium co pyright act. if such acts allow unauthorized access to your software or other copyrigh ted work, you may have a right to sue for relief under t hat act. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 1 pic16c62x devices included in this data sheet: referred to collectively as pic16c62x. pic16c620 pic16c620a pic16c621 pic16c621a pic16c622 pic16c622a pic16cr620a high performance risc cpu: only 35 instructions to learn all single cycle instructions (200 ns), except for program branches which are two-cycle operating speed: - dc - 40 mhz clock input - dc - 100 ns instruction cycle interrupt capability 16 special function hardware registers 8-level deep hardware stack direct, indirect and relative addressing modes peripheral features: 13 i/o pins with individual direction control high current sink/source for direct led drive analog comparator module with: - two analog comparators - programmable on-chip voltage reference (v ref ) module - programmable input multiplexing from device inputs and internal voltage reference - comparator outputs can be output signals timer0: 8-bit timer/counter with 8-bit programmable prescaler pin diagrams special microcontroller features: power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) brown-out reset watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode selectable oscillator options serial in-circuit programming (via two pins) four user programmable id locations cmos technology: low power, high speed cmos eprom technology fully static design wide operating range - 2.5v to 5.5v commercial, industrial and extended tempera- ture range low power consumption - < 2.0 ma @ 5.0v, 4.0 mhz -15 a typical @ 3.0v, 32 khz -< 1.0 a typical standby current @ 3.0v device program memory data memory pic16c620 512 80 pic16c620a 512 96 pic16cr620a 512 96 pic16c621 1k 80 pic16c621a 1k 96 pic16c622 2k 128 pic16c622a 2k 128 ra1/an1 ra0/an0 osc2/clkout v dd rb7 rb6 rb5 rb4 osc1/clkin ra2/an2/v ref ra3/an3 mclr/ v pp v ss rb0/int rb1 rb2 rb3 ra4/t0cki pic16c62x ra1/an1 ra0/an0 osc2/clkout v dd rb7 rb6 rb5 rb4 osc1/clkin ra2/an2/v ref ra3/an3 mclr/ v pp v ss v ss rb0/int rb1 rb2 ra4/t0cki rb3 rb3 v dd pdip, soic, windowed cerdip ssop 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 1 19 18 16 15 14 13 12 11 17 18 17 15 14 13 12 11 10 16 20 pic16c62x eprom-based 8-bit cmos microcontrollers downloaded from: http:///
pic16c62x ds30235j-page 2 ? 2003 microchip technology inc. device differences note 1: if you change from this device to another device, pl ease verify oscillator characteristics in your appl ication. 2: for rom parts, operation from 2.5v - 3.0v will requir e the pic16lcr62x parts. 3: for otp parts, operation from 2.5v - 3.0v will requi re the pic16lc62x parts. 4: for otp parts, operations from 2.7v - 3.0v will requ ire the pic16lc62xa parts. device voltage range oscillator process technology (microns) pic16c620 (3) 2.5 - 6.0 see note 1 0.9 pic16c621 (3) 2.5 - 6.0 see note 1 0.9 pic16c622 (3) 2.5 - 6.0 see note 1 0.9 pic16c620a (4) 2.7 - 5.5 see note 1 0.7 pic16cr620a (2) 2.5 - 5.5 see note 1 0.7 pic16c621a (4) 2.7 - 5.5 see note 1 0.7 pic16c622a (4) 2.7 - 5.5 see note 1 0.7 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 3 pic16c62x table of contents 1.0 general description ............................... ................................................... ....................... ................................................... ...... 5 2.0 pic16c62x device varieties ........................ ................................................... ....................... .................................................. 7 3.0 architectural overview .............................. ................................................... ..................... ................................................... ..... 9 4.0 memory organization .............................. ................................................... ....................... ................................................... .. 13 5.0 i/o ports....................................... ................................................... ......................... ................................................... ............ 25 6.0 timer0 module ................................... ................................................... ......................... ................................................... ...... 31 7.0 comparator module ............................... ................................................... ......................... ................................................... .. 37 8.0 voltage reference module ......................... ................................................... ........................ ................................................. 4 3 9.0 special features of the cpu ....................... ................................................... ....................... ................................................. 4 5 10.0 instruction set summary .......................... ................................................... ...................... ................................................... .. 61 11.0 development support ............................. ................................................... ........................ ................................................... .. 75 12.0 electrical specifications .......................... ................................................... .................... ................................................... ...... 81 13.0 device characterization information ............... ................................................... ..................... .............................................. 109 14.0 packaging information ............................ ................................................... ....................... ................................................... . 113 appendix a: enhancements............................. ................................................... ....................... ................................................... .... 119 appendix b: compatibility ........................... ................................................... ........................ ................................................... ........ 119 index .............................................. ................................................... ........................ ................................................... ................... 121 on-line support ................................... ................................................... ......................... ................................................... .............. 123 systems information and upgrade hot line .............. ................................................... ...................... .............................................. 123 reader response ...................................... ................................................... ....................... ................................................... .......... 124 product identification system .......................... ................................................... ..................... ................................................... ...... 125 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of you r micro - chip products. to this end, we will continue to improve our publications to better suit your needs. our publicati ons will be re fined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publica tion, please contact the marketing communications departm ent via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet , please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examinin g its literature number found on the bottom outside co rner of any page . the last character of the literature number is the versio n number, (e.g., ds30000a is version a of document ds30 000). errata an errata sheet, describing minor operational differen ces from the data sheet and recommended workarounds, may e xist for curren t devices. as device/documentation issues become known to us, we w ill publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de literature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products. downloaded from: http:///
pic16c62x ds30235j-page 4 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 5 pic16c62x 1.0 general description the pic16c62x devices are 18 and 20-pin rom/ eprom-based members of the versatile picmicro ? family of low cost, high performance, cmos, fully- static, 8-bit microcontrollers. all picmicro microcontrollers employ an advanced risc architecture. the pic16c62x devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. th e separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word w ith the separate 8-bit wide data. the two-stage instruc tion pipeline allows all instructions to execute in a si ngle cycle, except for program branches (which require tw o cycles). a total of 35 instructions (reduced instru ction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16c62x microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. the pic16c620a, pic16c621a and pic16cr620a have 96 bytes of ram. the pic16c622(a) has 128 bytes of ram. each device has 13 i/o pins and an 8- bit timer/counter with an 8-bit programmable prescaler . in addition, the pic16c62x adds two analog compara- tors with a programmable on-chip voltage reference module. the comparator module is ideally suited for applications requiring a low cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc). pic16c62x devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power con- sumption. there are four oscillator options, of whic h the single pin rc oscillator provides a low cost soluti on, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crys tals. the sleep (power-down) mode offers power savings. the user can wake-up the chip from sleep through several external and internal interrupts and reset. a highly reliable watchdog timer with its own on-chi p rc oscillator provides protection against software lock- up. a uv-erasable cerdip-packaged version is ideal for code development while the cost effective one-time- programmable (otp) version is suitable for production in any volume. table 1-1 shows the features of the pic16c62x mid- range microcontroller families. a simplified block diagram of the pic16c62x is shown in figure 3-1. the pic16c62x series fits perfectly in applications ranging from battery chargers to low power remote sensors. the eprom technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fas t and convenient. the small footprint packages make this microcontroller series perfect for all applicat ions with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the pic16c62x very versatile. 1.1 family and upward compatibility those users familiar with the pic16c5x family of microcontrollers will realize that this is an enhanc ed version of the pic16c5x architecture. please refer to appendix a for a detailed list of enhancements. code written for the pic16c5x can be easily ported to pic16c62x family of devices (appendix b). the pic16c62x family fills the niche for users wanting t o migrate up from the pic16c5x family and not needing various peripheral features of other members of the pic16xx mid-range microcontroller family. 1.2 development support the pic16c62x family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full-featured programmer. third party ?c? compilers ar e also available. downloaded from: http:///
pic16c62x ds30235j-page 6 ? 2003 microchip technology inc. table 1-1: pic16c62x family of devices pic16c620 (3) pic16c620a (1)(4) pic16cr620a (2) pic16c621 (3) pic16c621a (1)(4) pic16c622 (3) pic16c622a (1)(4) clock maximum frequency of operation (mhz) 20 40 20 20 40 20 40 memory eprom program memory (x14 words) 512 512 512 1k 1k 2k 2k data memory (bytes) 80 96 96 80 96 128 128 peripherals timer module(s) tmr0 tmr0 tmro tmr0 tmr0 tmr0 tmr0 comparators(s) 2 2 2 2 2 2 2 internal reference voltage yes yes yes yes yes yes yes features interrupt sources 4 4 4 4 4 4 4 i/o pins 13 13 13 13 13 13 13 voltage range (volts) 2.5-6.0 2.7-5.5 2.5-5.5 2.5-6.0 2.7-5.5 2. 5-6.0 2.7-5.5 brown-out reset yes yes yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all picmicro ? family devices have power-on reset, selectable watc hdog timer, selectable code protect and high i/o current capability. all pic16c62x family devices use serial programming with clock pin rb6 and data p in rb7. note 1: if you change from this device to another device, pl ease verify oscillator characteristics in your appl ication. 2: for rom parts, operation from 2.0v - 2.5v will requir e the pic16lcr62xa parts. 3: for otp parts, operation from 2.5v - 3.0v will requi re the pic16lc62x part. 4: for otp parts, operation from 2.7v - 3.0v will requi re the pic16lc62xa part. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 7 pic16c62x 2.0 pic16c62x device varieties a variety of frequency ranges and packaging options are available. depending on application and product ion requirements, the proper device option can be select ed using the information in the pic16c62x product identification system section at the end of this dat a sheet. when placing orders, please use this page of the data sheet to specify the correct part number. 2.1 uv erasable devices the uv erasable version, offered in cerdip package, is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the oscillator modes. microchip's picstart ? and pro mate ? programmers both support programming of the pic16c62x. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially usefu l for customers who need the flexibility for frequent code updates and small volume applications. in addition to the program memory, the configuration bits must also be programmed. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who chose not to program a medium to high quantity of units and whose code patterns h ave stabilized. the devices are identical to the otp devices, but with all eprom locations and configura- tion options already programmed by the factory. certain code and prototype verification procedures apply before production shipments are available. please contact your microchip technology sales offic e for more details. 2.4 serialized quick-turnaround- production sm (sqtp sm ) devices microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry-code, password or id number. note: microchip does not recommend code protecting windowed devices. downloaded from: http:///
pic16c62x ds30235j-page 8 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 9 pic16c62x 3.0 architectural overview the high performance of the pic16c62x family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16c62x uses a harvard architecture, in which, program and data are accessed from separate memories using separate busses. this improves bandwidth over traditional von neumann architecture, where program and data are fetched from the same memory. separating program and data memory further allows instructions to be sized differently than 8- bit wide data word. instruction opcodes are 14-bits wid e making it possible to have all single word instructi ons. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two-stage p ipeline overlaps fetch and execution of instructions. consequently, all instructions (35) execute in a si ngle cycle (200 ns @ 20 mhz) except for program branches. the pic16c620(a) and pic16cr620a address 512 x 14 on-chip program memory. the pic16c621(a) addresses 1k x 14 program memory. the pic16c622(a) addresses 2k x 14 program memory. all program memory is internal. the pic16c62x can directly or indirectly address it s register files or data memory. all special function registers including the program counter are mapped in the data memory. the pic16c62x has an orthogonal (symmetrical) instruction set that makes it possible t o carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic16c62x simple yet efficient. in addition, the learning curve is reduced significantly. the pic16c62x devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a file register o r an immediate constant. in single operand instructions, t he operand is either the w register or a file register . the w register is an 8-bit working register used fo r alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc ), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, bit in subtraction. see the sublw and subwf instructions for examples. a simplified block diagram is shown in figure 3-1, wit h a description of the device pins in table 3-1. downloaded from: http:///
pic16c62x ds30235j-page 10 ? 2003 microchip technology inc. figure 3-1: block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8-level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss voltage brown-out reset note 1: higher order bits are from the status register. device program memory data memory (ram) pic16c620 pic16c620a pic16cr620a pic16c621 pic16c621a pic16c622 pic16c622a 512 x 14 512 x 14 512 x 14 1k x 14 1k x 14 2k x 14 2k x 14 80 x 8 96 x 8 96 x 8 80 x 8 96 x 8 128 x 8 128 x 8 8 3 tmr0 i/o ports portb comparator ra3/an3 ra2/an2/v ref ra1/an1 ra0/an0 reference ra4/t0cki + - + - downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 11 pic16c62x table 3-1: pic16c62x pinout description name dip/soic pin # ssop pin # i/o/p type buffer type description osc1/clkin 16 18 i st/cmos oscillator crystal input/external clock source input. osc2/clkout 15 17 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin out- puts clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. mclr /v pp 4 4 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 17 19 i/o st analog comparator input ra1/an1 18 20 i/o st analog comparator input ra2/an2/v ref 1 1 i/o st analog comparator input or v ref output ra3/an3 2 2 i/o st analog comparator input /output ra4/t0cki 3 3 i/o st can be selected to be the clock input to the timer0 timer/counter or a comparator output. output is open drain type. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 6 7 i/o ttl/st (1) rb0/int can also be selected as an external interrupt pin. rb1 7 8 i/o ttl rb2 8 9 i/o ttl rb3 9 10 i/o ttl rb4 10 11 i/o ttl interrupt-on-change pin. rb5 11 12 i/o ttl interrupt-on-change pin. rb6 12 13 i/o ttl/st (2) interrupt-on-change pin. serial programming clock. rb7 13 14 i/o ttl/st (2) interrupt-on-change pin. serial programming data. v ss 5 5,6 p ? ground reference for logic and i/o pins. v dd 14 15,16 p ? positive supply for logic and i/o pins. legend: o = output i/o = input/output p = power ? = not used i = input st = schmitt trigger input ttl = ttl input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in ser ial programming mode. downloaded from: http:///
pic16c62x ds30235j-page 12 ? 2003 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divi ded by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2. 3.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q 1, q2, q3 and q4). the instruction fetch and execute a re pipelined such that fetch takes one instruction cyc le while decode and execute takes another instruction cycle. however, due to the pipelining, each instruc tion effectively executes in one cycle. if an instructio n causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruc tion (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register (ir)? in cycle q1. t his instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock note: all instructions are single cycle, except for any program bra nches. these take two cycles since the fetch instruction is ?flushed? from the pipeline, while the new instructi on is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 13 pic16c62x 4.0 memory organization 4.1 program memory organization the pic16c62x has a 13-bit program counter capable of addressing an 8k x 14 program memory space. only the first 512 x 14 (0000h - 01ffh) for the pic16c620(a) and pic16cr620, 1k x 14 (0000h - 03ffh) for the pic16c621(a) and 2k x 14 (0000h - 07ffh) for the pic16c622(a) are physically implemented. accessing a location above these boundaries will cause a wrap-around within the firs t 512 x 14 space (pic16c(r)620(a)) or 1k x 14 space (pic16c621(a)) or 2k x 14 space (pic16c622(a)). the reset vector is at 0000h and the interrupt vect or is at 0004h (figure 4-1, figure 4-2, figure 4-3). figure 4-1: program memory map and stack for the pic16c620/pic16c620a/ pic16cr620a figure 4-2: program memory map and stack for the pic16c621/pic16c621a figure 4-3: program memory map and stack for the pic16c622/pic16c622a pc<12:0> 13 000h 0004 0005 01ffh 0200h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, returnretfie, retlw stack level 2 pc<12:0> 13 000h 0004 0005 03ffh 0400h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, returnretfie, retlw stack level 2 pc<12:0> 13 000h 0004 0005 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, returnretfie, retlw stack level 2 downloaded from: http:///
pic16c62x ds30235j-page 14 ? 2003 microchip technology inc. 4.2 data memory organization the data memory (figure 4-4, figure 4-5, figure 4-6 and figure 4-7) is partitioned into two banks, which contain the general purpose registers and the speci al function registers. bank 0 is selected when the rp0 bit is cleared. bank 1 is selected when the rp0 bit (status <5>) is set. the special function registers are located in the first 32 locations of each bank. register locations 20-7fh (bank0) on the pic16c620a/cr620a/621a and 20-7fh (bank0) and a0-bfh (bank1) on the pic16c622 and pic16c622a are general purpose registers implemented as static ram. some special purpose registers are mapped in bank 1. addresses f0h-ffh of bank1 are implemented as common ram and mapped back to addresses 70h-7fh in bank0 on the pic16c620a/621a/622a/cr620a. 4.2.1 general purpose register file the register file is organized as 80 x 8 in the pic16c620/621, 96 x 8 in the pic16c620a/621a/ cr620a and 128 x 8 in the pic16c622(a). each is accessed either directly or indirectly through the file select register fsr (section 4.4). downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 15 pic16c62x figure 4-4: data memory map for the pic16c620/621 figure 4-5: data memory map for the pic16c622 indf (1) tmr0 pcl status fsr porta portb pclath intcon pir1 cmcon indf (1) option pcl status fsr trisa trisb pclath intcon pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address 6fh 70h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address indf (1) tmr0 pcl status fsr porta portb pclath intcon pir1 cmcon indf (1) option pcl status fsr trisa trisb pclath intcon pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address general purpose register downloaded from: http:///
pic16c62x ds30235j-page 16 ? 2003 microchip technology inc. figure 4-6: data memory map for the pic16c620a/cr620a/621a figure 4-7: data memory map for the pic16c622a indf (1) tmr0 pcl status fsr porta portb pclath intcon pir1 cmcon indf (1) option pcl status fsr trisa trisb pclath intcon pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address 6fh 70h file address accesses 70h-7fh f0h general purpose register unimplemented data memory locations, read as '0'. note 1: not a physical register. indf (1) tmr0 pcl status fsr porta portb pclath intcon pir1 cmcon indf (1) option pcl status fsr trisa trisb pclath intcon pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h file address general purpose register accesses 70h-7fh f0h 6fh 70h general purpose register unimplemented data memory locations, read as '0'. note 1: not a physical register. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 17 pic16c62x 4.2.2 special function registers the special function registers are registers used b y the cpu and peripheral functions for controlling th e desired operation of the device (table 4-1). these registers are static ram. the special function registers can be classified in to two sets (core and peripheral). the special functio n registers associated with the ?core? functions are described in this section. those related to the ope ration of the peripheral features are described in the sec tion of that peripheral feature. table 4-1: special registers for the pic16c62x address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets (1) bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 02h pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h status irp (2) rp1 (2) rp0 to pd z dc c 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta ? ? ? ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h-09h unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 ? cmif ? ? ? ? ? ? -0-- ---- -0-- ---- 0dh-1eh unimplemented ? ? 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl program counter's (pc) least significant byte 0000 0000 0000 0000 83h status irp (2) rp1 (2) rp0 to pd z dc c 0001 1xxx 000q quuu 84h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 87h-89h unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 ? cmie ? ? ? ? ? ? -0-- ---- -0-- ---- 8dh unimplemented ? ? 8eh pcon ? ? ? ? ? ? por bor ---- --0x ---- --uq 8fh-9eh unimplemented ? ? 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: other (non power-up) resets include mclr reset, brown-out reset and watchdog timer reset dur ing normal operation. 2: irp & rp1 bits are reserved; always maintain these b its clear. downloaded from: http:///
pic16c62x ds30235j-page 18 ? 2003 microchip technology inc. 4.2.2.1 status register the status register, shown in register 4-1, contains the arithmetic status of the alu, the reset status a nd the bank select bits for data memory. the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according t o the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction w ith the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status regi ster as 000uu1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bit. for other instructions not affecting any status bits, see the ?instruction set summary?. register 4-1: status register (address 03h or 83h) note 1: the irp and rp1 bits (status<7:6>) are not used by the pic16c62x and should be programmed as ?0'. use of these bits as general purpose r/w bits is not recommended, since this may affect upward compatibility with future products. 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. reserved reserved r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zd cc bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect address ing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) the irp bit is reserved on the pic16c62x; always mai ntain this bit clear. bit 6-5 rp<1:0> : register bank select bits (used for direct addres sing) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. the rp1 bit is reserved on the pic16c62x; always maintain this bit clear. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf, addlw,sublw,subwf instructions)(for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the res ult occurred 0 = no carry-out from the 4th low order bit of the re sult bit 0 c : carry/borrow bit ( addwf, addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the r esult occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is execute d by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 19 pic16c62x 4.2.2.2 option register the option register is a readable and writable register, which contains various control bits to co nfigure the tmr0/wdt prescaler, the external rb0/int interrupt, tmr0 and the weak pull-ups on portb. register 4-2: option register (address 81h) note: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt (psa = 1). r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port la tch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0> : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown 000001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate downloaded from: http:///
pic16c62x ds30235j-page 20 ? 2003 microchip technology inc. 4.2.2.3 intcon register the intcon register is a readable and writable register, which contains the various enable and fla g bits for all interrupt sources except the comparator modul e. see section 4.2.2.4 and section 4.2.2.5 for a description of the comparator enable and flag bits. register 4-3: intcon register (address 0bh or 8bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in s oftware) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit 1 = when at least one of the rb<7:4> pins changed st ate (must be cleared in software) 0 = none of the rb<7:4> pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 21 pic16c62x 4.2.2.4 pie1 register this register contains the individual enable bit fo r the comparator interrupt. register 4-4: pie1 register (address 8ch) 4.2.2.5 pir1 register this register contains the individual flag bit for the comparator interrupt. register 4-5: pir1 register (address 0ch) u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ? cmie ? ? ? ? ? ? bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6 cmie : comparator interrupt enable bit 1 = enables the comparator interrupt 0 = disables the comparator interrupt bit 5-0 unimplemented : read as '0' legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ? cmif ? ? ? ? ? ? bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6 cmif : comparator interrupt flag bit 1 = comparator input has changed 0 = comparator input has not changed bit 5-0 unimplemented : read as '0' legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown downloaded from: http:///
pic16c62x ds30235j-page 22 ? 2003 microchip technology inc. 4.2.2.6 pcon register the pcon register contains flag bits to differentia te between a power-on reset, an external mclr reset, wdt reset or a brown-out reset. register 4-6: pcon register (address 8eh) note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is cleared, indicating a brown-out has occurred. the bor status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?p o r bor bit 7 bit 0 bit 7-2 unimplemented: read as '0' bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in softwar e after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in softwa re after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 23 pic16c62x 4.3 pcl and pclath the program counter (pc) is 13-bits wide. the low by te comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 4-8 shows the two situations for the loading of the pc. the u pper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the figure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 4-8: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location cros ses a pcl memory boundary (each 256 byte block). refer to the application note, ?implementing a table read" (an556). 4.3.2 stack the pic16c62x family has an 8-level deep x 13-bit wide hardware stack (figure 4-2 and figure 4-3). the stack space is not part of either program or data sp ace and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the st ack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the nin th push overwrites the value that was stored from the f irst push. the tenth push overwrites the second push (an d so on). pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop . these are actions that occur from the execution of the call, return, retlw and retfie instructions, or the vectoring to an interrupt address. downloaded from: http:///
pic16c62x ds30235j-page 24 ? 2003 microchip technology inc. 4.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addre ssing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses data pointed to by the file selec t register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectl y results in a no-operation (although status bits may be affected). an effective 9-bit address is obtaine d by concatenating the 8-bit fsr register and the irp bi t (status<7>), as shown in figure 4-9. however, irp is not used in the pic16c62x. a simple program to clear ram location 20h-7fh using indirect addressing is shown in example 4-1. example 4-1: indirect addressing figure 4-9: direct/indirect addressing pic16c62x movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,7 ;all done? goto next ;no clear next ;yes continue continue: for memory map detail see (figure 4-4, figure 4-5, f igure 4-6 and figure 4-7). note 1: the rp1 and irp bits are reserved; always maintain t hese bits clear. data memory indirect addressing direct addressing bank select location select rp1 rp0 (1) 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 25 pic16c62x 5.0 i/o ports the pic16c62x have two ports, porta and portb. some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on t he device. in general, when a peripheral is enabled, t hat pin may not be used as a general purpose i/o pin. 5.1 porta and trisa registers porta is a 5-bit wide latch. ra4 is a schmitt trigge r input and an open drain output. port ra4 is multiple xed with the t0cki clock input. all other ra port pins have schmitt trigger input levels and full cmos output drivers. all pins have data direction bits (tris re gis- ters), which can configure these pins as input or o utput. a '1' in the trisa register puts the corresponding out- put driver in a hi-impedance mode. a '0' in the trisa register puts the contents of the output latch on t he selected pin(s). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. s o a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. the porta pins are multiplexed with comparator and voltage reference functions. the operation of these pins are selected by control bits in the cmcon (comparator control register) register and the vrcon (voltage reference control register) register. when selected as a comparator input, these pins will read as '0's. figure 5-1: block diagram of ra1:ra0 pins trisa controls the direction of the ra pins, even w hen they are being used as comparator inputs. the user must make sure to keep the pins configured as inputs when using them as comparator inputs. the ra2 pin will also function as the output for th e voltage reference. when in this mode, the v ref pin is a very high impedance output and must be buffered prior to any external load. the user must configure trisa<2> bit as an input and use high impedance loads. in one of the comparator modes defined by the cmcon register, pins ra3 and ra4 become outputs of the comparators. the trisa<4:3> bits must be cleared to enable outputs to use this function. example 5-1: initializing porta figure 5-2: block diagram of ra2 pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd i/o q d q ck input mode d q en to comparator schmitt trigger input buffer v dd pin v ss note: on reset, the trisa register is set to all inputs. the digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption. clrf porta ;initialize porta by setting ;output data latches movlw 0x07 ;turn comparators off and movwf cmcon ;enable pins for i/o ;functions bsf status, rp0 ;select bank1 movlw 0x1f ;value used to initialize ;data direction movwf trisa ;set ra<4:0> as inputs ;trisa<7:5> are always ;read as '0'. data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd ra2 q d q ck input mode d q en to comparator schmitt trigger input buffer v roe v ref v dd v ss pin downloaded from: http:///
pic16c62x ds30235j-page 26 ? 2003 microchip technology inc. figure 5-3: block diagram of ra3 pin figure 5-4: block diagram of ra4 pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd ra3 pin q d q ck d q en to comparator schmitt trigger input buffer input mode comparator output comparator mode = 110 v dd v ss data bus q d q ck n wr porta wr trisa data latch tris latch rd trisa rd porta v ss ra4 pin q d q ck d q en tmr0 clock input schmitt trigger input buffer comparator output comparator mode = 110 v ss downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 27 pic16c62x table 5-1: porta functions table 5-2: summary of registers associated with port a name bit # buffer type function ra0/an0 bit0 st input/output or comparator input ra1/an1 bit1 st input/output or comparator input ra2/an2/v ref bit2 st input/output or comparator input or v ref output ra3/an3 bit3 st input/output or comparator input/output ra4/t0cki bit4 st input/output or external clock input for tmr0 or comp arator output. output is open drain type. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 05h porta ? ? ? ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 85h trisa ? ? ? trisa 4 trisa 3 trisa 2 trisa 1 trisa 0 ---1 1111 ---1 1111 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: ? = unimplemented locations, read as ?0?, u = unchanged, x = unknown note: shaded bits are not used by porta. downloaded from: http:///
pic16c62x ds30235j-page 28 ? 2003 microchip technology inc. 5.2 portb and trisb registers portb is an 8-bit wide, bi-directional port. the corresponding data direction register is trisb. a ' 1' in the trisb register puts the corresponding output dr iver in a high impedance mode. a '0' in the trisb register puts the contents of the output latch on the select ed pin(s). reading portb register reads the status of the pins , whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a wr ite to a port implies that the port pins are first read, then this value is modified and written to the port data latch. each of the portb pins has a weak internal pull-up ( 200 a typical). a single control bit can turn on all th e pull-ups. this is done by clearing the rbpu (option<7>) bit. the weak pull-up is automatically turned off when the port pin is configured as an ou tput. the pull-ups are disabled on power-on reset. four of portb?s pins, rb<7:4>, have an interrupt on change feature. only pins configured as inputs can cause this interrupt to occur (e.g., any rb<7:4> pi n configured as an output is excluded from the interru pt on change comparison). the input pins (of rb<7:4>) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb<7:4> are or?ed together to generate the rbif interrupt ( flag latched in intcon<0>). figure 5-5: block diagram of rb<7:4> pins this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear t he interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rb if. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. this interrupt on mismatch feature, together with software configurable pull-ups on these four pins a llow easy interface to a key pad and make it possible for wake-up on key-depression. (see an552, ?implement- ing wake-up on key strokes.) the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on chang e feature. polling of portb is not recommended while using the interrupt-on-change feature. figure 5-6: block diagram of rb<3:0> pins data latch from other rbpu (1) p v dd i/o q d ck q d ck qd en qd en data bus wr portb wr trisb set rbif tris latch rd trisb rd portb rb<7:4> pins weak pull-up rd portb latch ttl input buffer pin note 1: trisb = 1 enables weak pull-up if rbpu = '0' (option<7>). st buffer rb<7:6> in serial programming mode q q v cc v ss note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt flag may not get set. data latch rbpu (1) p v dd q d ck d ck qd en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb rb0/int i/o pin ttl input buffer note 1: trisb = 1 enables weak pull-up if rbpu = '0' (option<7>). st buffer q q q v cc v ss downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 29 pic16c62x table 5-3: portb functions table 5-4: summary of registers associated with port b name bit # buffer type function rb0/int bit0 ttl/st (1) input/output or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software progr ammable weak pull-up. rb2 bit2 ttl input/output pin. internal software progr ammable weak pull-up. rb3 bit3 ttl input/output pin. internal software progr ammable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on-chang e). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on-chang e). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change). intern al software programmable weak pull-up. serial programming clock pin. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change). intern al software programmable weak pull-up. serial programming data pin. legend: st = schmitt trigger, ttl = ttl input note 1: this buffer is a schmitt trigger input when configur ed as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 06h portb r b 7 r b 6 r b 5r b 4r b 3r b 2r b 1r b 0 xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: u = unchanged, x = unknown note 1: shaded bits are not used by portb. downloaded from: http:///
pic16c62x ds30235j-page 30 ? 2003 microchip technology inc. 5.3 i/o programming considerations 5.3.1 bi-directional i/o ports any instruction which writes, operates internally a s a read followed by a write operation. the bcf and bsf instructions, for example, read the register into th e cpu, execute the bit operation and write the result back to the register. caution must be used when thes e instructions are applied to a port with both inputs and outputs defined. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be r ead into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/ o pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be rea d into the cpu and re-written to the data latch of this particular pin, overwriting the previous content. a s long as the pin stays in the input mode, no problem occurs . however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. reading the port register reads the values of the p ort pins. writing to the port register writes the value to the port latch. when using read-modify-write instruction s (ex. bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this valu e, and this value is then written to the port latch. example 5-2 shows the effect of two sequential read- modify-write instructions (ex., bcf, bsf , etc.) on an i/o port. a pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin (?wired-or?, ?wired -and?). the resulting high output currents may damage the chip. example 5-2: read-modify-write instructions on an i/o port 5.3.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data mus t be valid at the beginning of the instruction cycle (fi gure 5-7). therefore, care must be exercised if a write followe d by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow th e pin voltage to stabilize (load dependent) before the ne xt instruction which causes that file to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. whe n in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-7: successive i/o operation ; ; initial port settings: portb<7:4> inputs ; portb<3:0> outputs ; ; portb<7:6> have external pull-up and are not connected to other circuitry ; ; port latch port pins ; ---------- --------- - bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bsf status,rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ; note that the user may have expected the pin ; values to be 00pp pppp. the 2nd bcf caused ; rb7 to be latched as the pin value (high). note: this example shows write to portb followed by a read from portb. note that: data setup time = (0.25 t cy - t pd ) where t cy = instruction cycle and tpd = propagation delay of q1 cycle to output valid. therefore, at higher clock frequen- cies, a write followed by a read may be problematic. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 rb <7:0> port pin sampled here pc pc + 1 pc + 2 pc + 3 nop nop movf portb, w read portb movwf portb write to portb pc instruction fetched t pd execute movwf portb execute movf portb, w execute nop rb<7:0> pc pc+1 pc+2 pc+3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 nop nop movf, portb, w read portb movwf, portb write to portb port pin sampled here t pd execute movwf portb execute movf portb, w execute nop pc instruction fetched downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 31 pic16c62x 6.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the tmr0 will increment every instruction cycle (without prescaler). if time r0 is written, the increment is inhibited for the followin g two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to tmr0. counter mode is selected by setting the t0cs bit. in this mode, timer0 will increment either on every risin g or falling edge of pin ra4/t0cki. the incrementing edge is determined by the source edge (t0se) control bit (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock inp ut are discussed in detail in section 6.2. the prescaler is shared between the timer0 module and the watchdog timer. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable o r writable. when the prescaler is assigned to the time r0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. section 6.3 details the operation of the prescaler. 6.1 timer0 interrupt timer0 interrupt is generated when the tmr0 register timer/counter overflows from ffh to 00h. this overflo w sets the t0if bit. the interrupt can be masked by clearing the t0ie bit (intcon<5>). the t0if bit (intcon<2>) must be cleared in software by the timer0 module interrupt service routine before re- enabling this interrupt. the timer0 interrupt cannot wake the processor from sleep, since the timer is shu t off during sleep. see figure 6-4 for timer0 interrupt timing. figure 6-1: timer0 block diagram figure 6-2: timer0 (tmr0) timing: internal clock/no prescaler note 1: bits t0se, t0cs, ps2, ps1, ps0 and psa are located in the option register. 2: the prescaler is shared with watchdog timer (figure 6 -6). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 tcy delay) psout data bus 8 set flag bit t0if on overflow psa ps<2:0> pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0+1 nt0+2 t0 movwf tmr0 movf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed downloaded from: http:///
pic16c62x ds30235j-page 32 ? 2003 microchip technology inc. figure 6-3: timer0 timing: internal clock/prescale 1 :2 figure 6-4: timer0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,wmovf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout(3) tmr0 timer t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction flow pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h note 1: t0if interrupt flag is sampled here (every q1). 2: interrupt latency = 3t cy , where t cy = instruction cycle time. 3: clkout is available only in rc oscillator mode. interrupt latency time(2) downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 33 pic16c62x 6.2 using timer0 with external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actu al incrementing of timer0 after synchronization. 6.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronizatio n of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki t o be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler, so that the prescaler output is symmetrica l. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. therefore, it is necessary for t0cki to ha ve a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not viola te the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical specifica tion of the desired device. 6.2.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the tmr0 is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. figure 6-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling note 1: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval betwee n two edges on timer0 input = 4tosc max. 2: external clock if no prescaler selected, prescaler output oth erwise. 3: the arrows indicate the points in time where sampling occurs. (3) (1) downloaded from: http:///
pic16c62x ds30235j-page 34 ? 2003 microchip technology inc. 6.3 prescaler an 8-bit counter is available as a prescaler for th e timer0 module, or as a postscaler for the watchdog timer, respectively (figure 6-6). for simplicity, this counter is being referred to as ?prescaler? through out this data sheet. note that there is only one presca ler available which is mutually exclusive between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer an d vice-versa. the psa and ps<2:0> bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. figure 6-6: block diagram of the timer0/wdt prescale r t0cki t0se pin m u x clkout (= fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0se, t0cs, psa, ps<2:0> are bits in the option regi ster. psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 35 pic16c62x 6.3.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? durin g program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to wdt. ) example 6-1: changing prescaler (timer0 wdt) to change prescaler from the wdt to the tmr0 module, use the sequence shown in example 6-2. this precaution must be taken even if the wdt is disabled . example 6-2: changing prescaler (wdt timer0) table 6-1: registers associated with timer0 1.bcf status, rp0 ;skip if already in ;bank 0 2.clrwdt ;clear wdt 3.clrf tmr0 ;clear tmr0 & prescaler 4.bsf status, rp0 ;bank 1 5.movlw '00101111?b; ;these 3 lines (5, 6, 7) 6.movwf option ;are required only if ;desired ps<2:0> are 7.clrwdt ;000 or 001 8.movlw '00101xxx?b ;set postscaler to 9.movwf option ;desired wdt rate 10.bcf status, rp0 ;return to bank 0 clrwdt ;clear wdt and ;prescaler bsf status, rp0 movlw b'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source movwf option_reg bcf status, rp0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 01h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: ? = unimplemented locations, read as ?0?, u = unchanged, x = unknown note: shaded bits are not used by tmr0 module. downloaded from: http:///
pic16c62x ds30235j-page 36 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 37 pic16c62x 7.0 comparator module the comparator module contains two analog comparators. the inputs to the comparators are multiplexed with the ra0 through ra3 pins. the on- chip voltage reference (section 8.0) can also be an input to the comparators. the cmcon register, shown in register 7-1, controls the comparator input and output multiplexers. a block diagram of the comparator is shown in figure 7-1. register 7-1: cmcon register (address 1fh) r-0 r-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out ? ? cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - bit 6 c1out : comparator 1 output 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - bit 5-4 unimplemented: read as ?0? bit 3 cis : comparator input switch when cm<2:0>: = 001: 1 = c1 v in - connects to ra3 0 = c1 v in - connects to ra0 when cm<2:0> = 010: 1 = c1 v in - connects to ra3 c2 v in - connects to ra2 0 = c1 v in - connects to ra0 c2 v in - connects to ra1 bit 2-0 cm<2:0> : comparator mode. legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown downloaded from: http:///
pic16c62x ds30235j-page 38 ? 2003 microchip technology inc. 7.1 comparator configuration there are eight modes of operation for the comparators. the cmcon register is used to select the mode. figure 7-1 shows the eight possible modes. the trisa register controls the data direction of t he comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in table 12-2. figure 7-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change other- wise a false interrupt may occur. - + c1 v in - v in + off (read as '0') ra0/an0 ra3/an3 a a cm<2:0> = 000 - + c2 v in - v in + off (read as '0') ra1/an1 ra2/an2 a a - + c1 v in - v in + off (read as '0') ra0/an0 ra3/an3 d d cm<2:0> = 111 - + c2 v in - v in + off (read as '0') ra1/an1 ra2/an2 d d - + c1 v in - v in + c1out ra0/an0 ra3/an3 a a - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm<2:0> = 100 - + c1 v in - v in + c1out ra0/an0 ra3/an3 a a - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a from v ref module - + c1 v in - v in + c1out ra0/an0 ra3/an3 a d - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm<2:0> = 011 ra4 open drain - + c1 v in - v in + c1out ra0/an0 ra3/an3 a d - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm<2:0> = 110 - + c1 v in - v in + off (read as '0') ra0/an0 ra3/an3 d d cm<2:0> = 101 - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a - + c1 v in - v in + c1out ra0/an0 ra3/an3 a a - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm<2:0> = 001 cis=0 cis=1 comparators reset two independent comparators two common reference comparators one independent comparator three inputs multiplexed to two common reference comparators with outputs four inputs multiplexed to comparators off two comparators two comparators cm<2:0> = 010 cis=0 cis=1 cis=0 cis=1 a = analog input, port reads zeros always d = digital input cis = cmcon<3>, comparator input switch downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 39 pic16c62x the code example in example 7-1 depicts the steps required to configure the comparator module. ra3 and ra4 are configured as digital output. ra0 and ra1 a re configured as the v- inputs and ra2 as the v+ input to both comparators. example 7-1: initializing comparator module 7.2 comparator operation a single comparator is shown in figure 7-2 along with the relationship between the analog input levels an d the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 7-2 represent the uncertainty due to input offsets and response t ime. 7.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal that is present at v in - is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly (figure 7-2). figure 7-2: single comparator 7.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd , and can be applied to either pin of the comparator(s). 7.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. section 10, instruction sets, contains a detailed description of the voltage reference module that provides this signal. the internal reference s ignal is used when the comparators are in mode cm<2:0>=010 (figure 7-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. movlw 0x03 ;init comparator mode movwf cmcon ;cm<2:0> = 011 clrf porta ;init porta bsf status,rp0 ;select bank1 movlw 0x07 ;initialize data direction movwf trisa ;set ra<2:0> as inputs ;ra<4:3> as outputs ;trisa<7:5> always read ?0? bcf status,rp0 ;select bank 0 call delay 10 ;10 s delay movf cmcon,f ;read cmcon to end change condition bcf pir1,cmif ;clear pending interrupts bsf status,rp0 ;select bank 1 bsf pie1,cmie ;enable comparator interrupts bcf status,rp0 ;select bank 0 bsf intcon,peie ;enable peripheral interrupts bsf intcon,gie ;global interrupt enable v inC v in+ utput ? + v in + v in - output output v in + v in - downloaded from: http:///
pic16c62x ds30235j-page 40 ? 2003 microchip technology inc. 7.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise the maximum delay of the comparators should be used (table 12-2). 7.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read only. the comparator outputs may also be directly output to the ra3 and r a4 i/o pins. when the cm<2:0> = 110, multiplexors in the output path of the ra3 and ra4 pins will switch and the output of each pin will be the unsynchronized outpu t of the comparator. the uncertainty of each of the comparators is related to the input offset voltage a nd the response time given in the specifications. figure 7-3 shows the comparator output block diagram. the trisa bits will still function as an output ena ble/ disable for the ra3 and ra4 pins while in this mode. figure 7-3: comparator output block diagram note 1: when reading the port register, all pins configured as analog inputs will read as a ?0?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. d q en to ra3 or ra4 pin bus data rd cmcon set multiplex cmif bit - + d q en cl p ort p ins rd cmcon nreset f rom o ther c omparator downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 41 pic16c62x 7.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, t o determine the actual change that has occurred. the cmif bit, pir1<6>, is the comparator interrupt flag. the cmif bit must be reset by clearing ?0?. since it is also possible to write a '1' to this register, a si mulated interrupt may be initiated. the cmie bit (pie1<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of th ese bits are clear, the interrupt is not enabled, thoug h the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can cle ar the interrupt in the following manner: a) any read or write of cmcon. this will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmi f. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. 7.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interr upt will wake up the device from sleep mode when enabled. while the comparator is powered-up, higher sleep currents than shown in the power-down current specification will occur. each comparator that is operational will consume additional current as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111, before entering sleep. if the device wakes up from sleep, the contents of t he cmcon register are not affected. 7.8 effects of a reset a device reset forces the cmcon register to its reset state. this forces the comparator module to be in the comparator reset mode, cm<2:0> = 000. this ensures that all potential inputs are analog inputs . device current is minimized when analog inputs are present at reset time. the comparators will be powered-down during the reset interval. 7.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 7-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latchup may occur. a maximum source impedance of 10 k is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very litt le leakage current. figure 7-4: analog input model note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir1<6>) interrupt flag may not get set. va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctio ns r ic = interconnect resistance r s = source impedance va = analog voltage downloaded from: http:///
pic16c62x ds30235j-page 42 ? 2003 microchip technology inc. table 7-1: registers associated with comparator modu le legend: x = unknown, u = unchanged, - = unimplemented, read as "0" address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 ? cmif ? ? ? ? ? ? -0-- ---- -0-- ---- 8ch pie1 ? cmie ? ? ? ? ? ? -0-- ---- -0-- ---- 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 43 pic16c62x 8.0 voltage reference module the voltage reference is a 16-tap resistor ladder network that provides a selectable voltage referenc e. the resistor ladder is segmented to provide two rang es of v ref values and has a power-down function to conserve power when the reference is not being used . the vrcon register controls the operation of the reference as shown in register 8-1. the block diagra m is given in figure 8-1. 8.1 configuring the voltage reference the voltage reference can output 16 distinct voltag e levels for each range. the equations used to calcul ate the output of the voltage reference are as follows: if v rr = 1: v ref = (v r <3:0>/24) x v dd if v rr = 0: v ref = (v dd x 1/4) + (v r <3:0>/32) x v dd the setting time of the voltage reference must be considered when changing the v ref output (table 12-1). example 8-1 shows an example of how to configure the voltage reference for an output voltage of 1.25v wi th v dd = 5.0v. register 8-1: vrcon register(address 9fh) figure 8-1: voltage reference block diagram r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 v ren v roe v rr ?v r 3v r 2v r 1v r 0 bit 7 bit 0 bit 7 v ren : v ref enable 1 = v ref circuit powered on 0 = v ref circuit powered down, no i dd drain bit 6 v roe : v ref output enable 1 = v ref is output on ra2 pin 0 = v ref is disconnected from ra2 pin bit 5 v rr : v ref range selection 1 = low range 0 = high range bit 4 unimplemented: read as '0' bit 3-0 v r <3:0> : v ref value selection 0 v r [3:0] 15 when v rr = 1: v ref = (v r <3:0>/ 24) * v dd when v rr = 0: v ref = 1/4 * v dd + (v r <3:0>/ 32) * v dd legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? - n = value at por ?1? = bit is set ?0? = bit is clea red x = bit is unknown note: r is defined in table 12-2. v rr 8r v r 3 v r 0 (from vrcon<3:0>) 16-1 analog mux 8r r r r r v ren v ref 16 stages downloaded from: http:///
pic16c62x ds30235j-page 44 ? 2003 microchip technology inc. example 8-1: voltage reference configuration 8.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to the construction of the module. the transistors on the t op and bottom of the resistor ladder network (figure 8-1 ) keep v ref from approaching v ss or v dd . the voltage reference is v dd derived and therefore, the v ref output changes with fluctuations in v dd . the tested absolute accuracy of the voltage reference can be found in table 12-2. 8.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the vrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 8.4 effects of a reset a device reset disables the voltage reference by clearing bit v ren (vrcon<7>). this reset also disconnects the reference from the ra2 pin by cleari ng bit v roe (vrcon<6>) and selects the high voltage range by clearing bit v rr (vrcon<5>). the v ref value select bits, vrcon<3:0>, are also cleared. 8.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the ra2 pin if the trisa<2> bit is set and the v roe bit, vrcon<6>, is set. enabling the voltage reference output onto the ra2 pin with an input signal present will increase current consumption. connecting ra2 as a digital output with v ref enabled will also increase current consumption. the ra2 pin can be used as a simple d/a output with limited drive capability. due to the limited drive capability, a buffer must be used in conjunction wit h the voltage reference output for external connections t o v ref . figure 8-2 shows an example buffering technique. figure 8-2: voltage reference output buffer example table 8-1: registers associated with voltage referen ce note: - = unimplemented, read as "0" movlw 0x02 ; 4 inputs muxed movwf cmcon ; to 2 comps. bsf status,rp0 ; go to bank 1 movlw 0x0f ; ra3-ra0 are movwf trisa ; inputs movlw 0xa6 ; enable v ref movwf vrcon ; low range ; set v r <3:0>=6 bcf status,rp0 ; go to bank 0 call delay10 ; 10 s delay address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9fh vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 1fh cmcon c2out c1out ? ? cis cm2 cm1 cm0 00-- 0000 00-- 0000 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 v ref output + ? v ref module voltage reference output impedance r (1) ra note 1: r is dependent upon the voltage reference configura tion vrcon<3:0> and vrcon<5>. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 45 pic16c62x 9.0 special features of the cpu special circuits to deal with the needs of real-time applications are what sets a microcontroller apart f rom other processors. the pic16c62x family has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offe r code protection. these are: 1. osc selection 2. reset power-on reset (por) power-up timer (pwrt) oscillator start-up timer (ost) brown-out reset (bor) 3. interrupts 4. watchdog timer (wdt) 5. sleep 6. code protection 7. id locations 8. in-circuit serial programming? the pic16c62x devices have a watchdog timer which is controlled by configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to kee p the chip in reset until the crystal oscillator is s table. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. there is also circuitry to reset the device if a brown-out occurs, which pro- vides at least a 72 ms reset. with these three functions on-chip, most applications need no externa l reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves sys tem cost, while the lp crystal option saves power. a se t of configuration bits are used to select various optio ns. downloaded from: http:///
pic16c62x ds30235j-page 46 ? 2003 microchip technology inc. 9.1 configuration bits the configuration bits can be programmed (read as '0' ) or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in program memory location 2007h. the user will note that address 2007h is bey ond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h ? 3fffh), which can be accessed only during programming. register 9-1: configuration word (address 2007h) cp1 cp0 (2) cp1 cp0 (2) cp1 cp0 (2) boden cp1 cp0 (2) pwrte wdte f0sc1 f0sc0 bit 13 bit 0 bit 13-8, 5-4: cp<1:0>: code protection bit pairs (2) code protection for 2k program memory 11 = program memory code protection off 10 = 0400h-07ffh code protected 01 = 0200h-07ffh code protected 00 = 0000h-07ffh code protected code protection for 1k program memory 11 = program memory code protection off 10 = program memory code protection off 01 = 0200h-03ffh code protected 00 = 0000h-03ffh code protected code protection for 0.5k program memory 11 = program memory code protection off 10 = program memory code protection off 01 = program memory code protection off 00 = 0000h-01ffh code protected bit 7 unimplemented : read as ?0? bit 6 boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3 pwrte : power-up timer enable bit (1, 3) 1 = pwrt disabled 0 = pwrt enabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power -up timer (pwrt) regardless of the value of bit pwrte . ensure the power-up timer is enabled anytime brown- out detect reset is enabled. 2: all of the cp<1:0> pairs have to be given the same v alue to enable the code protection scheme listed. 3: unprogrammed parts default the power-up timer disabled . legend: r = readable bit w = writable bit u = unimplemented bit , read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 47 pic16c62x 9.2 oscillator configurations 9.2.1 oscillator types the pic16c62x devices can be operated in four different oscillator options. the user can program t wo configuration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 9.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation (figure 9-1). the pic16c62x oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1 pin (figure 9-2). figure 9-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 9-2: external clock input operation (hs, xt or lp osc configuration) table 9-1: capacitor selection for ceramic resonators table 9-2: capacitor selection for crystal oscillator see table 9-1 and table 9-2 for recommended values of c1 and c2. note: a series resistor may be required for at strip cut crystals. c1 c2 xtal osc2 rs osc1 rf sleep to internal logic pic16c62x see note clock from ext. system pic16c62x osc1 osc2 open ranges characterized: mode freq osc1(c1) osc2(c2) xt 455 khz 2.0 mhz 4.0 mhz 22 - 100 pf 15 - 68 pf 15 - 68 pf 22 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf higher capacitance increases the stability of the oscil- lator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. mode freq osc1(c1) osc2(c2) lp 32 khz 200 khz 68 - 100 pf 15 - 30 pf 68 - 100 pf 15 - 30 pf xt 100 khz 2 mhz 4 mhz 68 - 150 pf 15 - 30 pf 15 - 30 pf 150 - 200 pf 15 - 30 pf 15 - 30 pf hs 8 mhz 10 mhz 20 mhz 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. downloaded from: http:///
pic16c62x ds30235j-page 48 ? 2003 microchip technology inc. 9.2.3 external crystal oscillator circuit either a prepackaged oscillator can be used or a si mple oscillator circuit with ttl gates can be built. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used; one with series resonance or one with paralle l resonance. figure 9-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180 phase shift that a parallel oscillator requires. the 4.7 k resistor provides the negative feedback for stability. the 10 k potentiometers bias the 74as04 in the linear region. this could be used for external oscillator designs. figure 9-3: external parallel resonant crystal oscillator circuit figure 9-4 shows a series resonant oscillator circui t. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 18 0 phase shift in a series resonant oscillator circuit . the 330 k resistors provide the negative feedback to bias the inverters in their linear region. figure 9-4: external series resonant crystal oscillator circuit 9.2.4 rc oscillator for timing insensitive applications the ?rc? device option offers additional cost savings. the rc oscil lator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values, and the operating temperature. in addition to this, the osci llator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of ext ernal r and c components used. figure 9-5 shows how the r/c combination is connected to the pic16c62x. for r ext values below 2.2 k , the oscillator operation may become unstable or stop completely. for very high r ext values (e.g., 1 m ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend to keep r ext between 3 k and 100 k . although the oscillator will operate with no extern al capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with n o or small external capacitance, the oscillation frequenc y can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. see section 13.0 for rc frequency variation from part to part due to normal process variation. the variati on is larger for larger r (since leakage current variatio n will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). see section 13.0 for variation of oscillator frequen cy due to v dd for given r ext /c ext values, as well as frequency variation due to operating temperature for given r, c and v dd values. the oscillator frequency, divided by 4, is availabl e on the osc2/clkout pin, and can be used for test purposes or to synchronize other logic (figure 3-2 f or waveform). figure 9-5: rc oscillator mode 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c62x clk in to other devices 330 k 74as04 74as04 pic16c62x clk in to other devices xtal 330 k 74as04 0.1 f osc2/clkout c ext r ext v dd pic16c62x osc1 f osc /4 internal clock v dd downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 49 pic16c62x 9.3 reset the pic16c62x differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt reset (normal operation) e) wdt wake-up (sleep) f) brown-out reset (bor) some registers are not affected in any reset condition their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset, mclr reset, wdt reset and mclr reset during sleep. they are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations as indicated in table 9-2. these bits are used in software to determine the nat ure of the reset. see table 9-5 for a full description o f reset states of all registers. a simplified block diagram of the on-chip reset circu it is shown in figure 9-6. the mclr reset path has a noise filter to detect and ignore small pulses. see table 12-5 for pulse width specification. figure 9-6: simplified block diagram of on-chip rese t circuit s r q external reset mclr / v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt time-out power-on reset ost pwrt chip_reset 10-bit ripple-counter reset enable ost enable pwrt sleep see table 9-1 for time-out situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden clkin pin v pp pin 10-bit ripple-counter q downloaded from: http:///
pic16c62x ds30235j-page 50 ? 2003 microchip technology inc. 9.4 power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost) and brown-out reset (bor) 9.4.1 power-on reset (por) the on-chip por circuit holds the chip in reset unt il v dd has reached a high enough level for proper operation. to take advantage of the por, just tie the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create power-on reset. a maximum rise time for v dd is required. see electrical specifications for details . the por circuit does not produce an internal reset when v dd declines. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, t he device must be held in reset until the operating conditions are met. for additional information, refer to application not e an607, ?power-up trouble shooting?. 9.4.2 power-up timer (pwrt) the power-up timer provides a fixed 72 ms (nominal) time-out on power-up only, from por or brown-out reset. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as pw rt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit, pwrte can disable (if set) or enable (if cleared or programmed) the power-up timer. the power-up timer should always be enabled when brown-out reset is enabled. the power-up time delay will vary from chip-to-chip and due to v dd , temperature and process variation. see dc parameters for details. 9.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 9.4.4 brown-out reset (bor) the pic16c62x members have on-chip brown-out reset circuitry. a configuration bit, boden, can disable (if clear/programmed) or enable (if set) the brown-out reset circuitry. if v dd falls below 4.0v refer to v bor parameter d005 (v bor ) for greater than parameter (t bor ) in table 12-5. the brown-out situa- tion will reset the chip. a reset won?t occur if v dd falls below 4.0v for less than parameter (t bor ). on any reset (power-on, brown-out, watchdog, etc.) the chip will remain in reset until v dd rises above bv dd . the power-up timer will now be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out res et and the power-up timer will be re-initialized. once v dd rises above bv dd , the power-up timer will execute a 72 ms reset. the power-up timer should always be enabled when brown-out reset is enabled. figure 9-7 shows typical brown-out situations. figure 9-7: brown-out situations 72 ms bv dd v dd internal reset bv dd v dd internal reset 72 ms <72 ms 72 ms bv dd v dd internal reset downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 51 pic16c62x 9.4.5 time-out sequence on power-up the time-out sequence is as follows: fir st pwrt time-out is invoked after por has expired. then ost is activated. the total time-out will vary based on oscillator configuration and pwrte bit status. for example, in rc mode with pwrte bit erased (pwrt disabled), there will be no time-out at all. figure 9 -8, figure 9-9 and figure 9-10 depict time-out sequences. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (see figure 9-9). this is useful for testing purpose s or to synchronize more than one pic16c62x device operating in parallel. table 9-4 shows the reset conditions for some special registers, while table 9-5 shows the reset conditions for all the registers. 9.4.6 power control (pcon)/ status register the power control/status register, pcon (address 8eh), has two bits. bit0 is bor (brown-out). bor is unknown on power- on reset. it must then be set by the user and checke d on subsequent resets to see if bor = 0, indicating that a brown-out has occurred. the bor status bit is a don?t care and is not necessarily predictable if the brown-out circuit is disabled (by setting boden bit = 0 in the configuration word). bit1 is por (power-on reset). it is a ?0? on power-on reset and unaffected otherwise. the user must write a ?1? to this bit following a power-on reset. on a subsequent reset, if por is ?0?, it will indicate that a power-on reset must have occurred (v dd may have gone too low). table 9-1: time-out in various situations table 9-2: status/pcon bits and their significance legend: u = unchanged, x = unknown oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms ? 72 ms ? por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 10xx brown-out reset 110u wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep table 9-3: summary of registers associated with brow n-out address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets (1) 83h status to pd 0001 1xxx 000q quuu 8eh pcon ? ? ? ? ? ?p o r bor ---- --0x ---- --uq legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition. note 1: other (non power-up) resets include mclr reset, brown-out reset and watchdog timer reset dur ing normal operation. downloaded from: http:///
pic16c62x ds30235j-page 52 ? 2003 microchip technology inc. table 9-4: initialization condition for special regi sters table 9-5: initialization condition for registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 uuuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 000x xuuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?. note 1: when the wake-up is due to an interrupt and global enable bit, gie is set, the pc is loaded with the interrupt vector (0004h) after execution of pc+1. register address power-on reset mclr reset during normal operation mclr reset during sleep wdt reset brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time-out w ? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h ? ? ? tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000 0000 0000 0000 pc + 1 (3) status 03h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h ---x xxxx ---u uuuu ---u uuuu portb 06h xxxx xxxx uuuu uuuu uuuu uuuu cmcon 1fh 00-- 0000 00-- 0000 uu-- uuuu pclath 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uqqq (2) pir1 0ch -0-- ---- -0-- ---- -q-- ---- (2,5) option 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h ---1 1111 ---1 1111 ---u uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu pie1 8ch -0-- ---- -0-- ---- -u-- ---- pcon 8eh ---- --0x ---- --uq (1,6) ---- --uu vrcon 9fh 000- 0000 000- 0000 uuu- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and reg isters will be affected differently. 2: one or more bits in intcon, pir1 and/or pir2 will b e affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie b it is set, the pc is loaded with the interrupt vector (00 04h). 4: see table 9-4 for reset value for specific condition. 5: if wake-up was due to comparator input changing, then b it 6 = 1. all other interrupts generating a wake-up w ill cause bit 6 = u. 6: if reset was due to brown-out, then bit 0 = 0. all o ther resets will cause bit 0 = u. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 53 pic16c62x figure 9-8: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 9-9: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 9-10: time-out sequence on power-up (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset downloaded from: http:///
pic16c62x ds30235j-page 54 ? 2003 microchip technology inc. figure 9-11: external power-on reset circuit (for slow v dd power-up) figure 9-12: external brown-out protection circuit 1 figure 9-13: external brown-out protection circuit 2 figure 9-14: external brown-out protection circuit 3 note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: < 40 k is recommended to make sure that voltage drop across r does not violate the device?s electrical specifica- tion. 3: r1 = 100 to 1 k will limit any current flowing into mclr from external capaci- tor c in the event of mclr/ v pp pin breakdown due to electrostatic discharge (esd) or electrical over- stress (eos). c r1 r d v dd mclr pic16c62x v dd note 1: this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. 2: internal brown-out reset circuitry should be disabled when using this circuit. v dd 33k 10k 40k v dd mclr pic16c62x note 1: this brown-out circuit is less expen- sive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: internal brown-out reset should be disabled when using this circuit. 3: resistors should be adjusted for the characteristics of the transistor. v dd x r1 r1 + r2 = 0.7v v dd r2 40k v dd mclr pic16c62x r1 q1 this brown-out protection circuit employs microchip technology?s mcp809 microcontroller supervisor. the mcp8xx and mcp1xx families of supervisors provide push-pull and open collector outputs with both high and low active reset pins. there are 7 different trip point selections to accommodate 5v and 3v systems. mclr pic16c62x v dd vss rst mcp809 v dd bypass capacitor v dd downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 55 pic16c62x 9.5 interrupts the pic16c62x has 4 sources of interrupt: external interrupt rb0/int tmr0 overflow interrupt portb change interrupts (pins rb<7:4>) comparator interrupt the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disable s (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register. gie is cleared on reset. the ?return from interrupt? instruction, retfie , exits interrupt routine, as well as sets the gie bit, whi ch re- enable rb0/int interrupts. the int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in t he intcon register. the peripheral interrupt flag is contained in the s pecial register pir1. the corresponding interrupt enable b it is contained in special registers pie1. when an interrupt is responded to, the gie is clear ed to disable any further interrupt, the return addres s is pushed into the stack and the pc is loaded with 000 4h. once in the interrupt service routine, the source(s ) of the interrupt can be determined by polling the inter rupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid rb0 / int recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs (figure 9-16 ). the latency is the same for one or two cycle instructions. once in the interrupt service routine , the source(s) of the interrupt can be determined by poll ing the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts t o avoid multiple interrupt requests. figure 9-15: interrupt logic note 1: individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the cpu will execute a nop in the cycle immediately following the instruction which clears the gie bit. the interrupts which were ignored are still pending to be serviced when the gie bit is set again. rbif rbie t0if t0ie intf inte gie peie wake-up (if in sleep mode) interrupt to cpu cmie cmif downloaded from: http:///
pic16c62x ds30235j-page 56 ? 2003 microchip technology inc. 9.5.1 rb0/int interrupt external interrupt on rb0/int pin is edge triggered , either rising if intedg bit (option<6>) is set, or fall- ing, if intedg bit is clear. when a valid edge appe ars on the rb0/int pin, the intf bit (intcon<1>) is set . this interrupt can be disabled by clearing the inte control bit (intcon<4>). the intf bit must be cleare d in software in the interrupt service routine before re- enabling this interrupt. the rb0/int interrupt can wake-up the processor from sleep, if the inte bit wa s set prior to going into sleep. the status of the gi e bit decides whether or not the processor branches to th e interrupt vector following wake-up. see section 9.8 for details on sleep and figure 9-18 for timing of wake- up from sleep through rb0/int interrupt. 9.5.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set the t0if (intcon<2>) bit. the interrupt can be enabled/disabled by setting/clearing t0ie (intcon<5>) bit. for operation of the timer0 module, see section 6.0. 9.5.3 portb interrupt an input change on portb <7:4> sets the rbif (intcon<0>) bit. the interrupt can be enabled/dis- abled by setting/clearing the rbie (intcon<4>) bit. for operation of portb (section 5.2). 9.5.4 comparator interrupt see section 7.6 for complete description of comparator interrupts. figure 9-16: int pin interrupt timing note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif interrupt flag may not get set. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? 1 4 5 1 2 3 note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a two-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set anytime during the q4-q1 cycles. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 57 pic16c62x table 9-6: summary of interrupt registers 9.6 context saving during interrupts during an interrupt, only the return pc value is sa ved on the stack. typically, users may wish to save key registers during an interrupt (e.g., w register and status register). this will have to be implemented in software. example 9-3 stores and restores the status and w registers. the user register, w_temp, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., w_temp is defined at 0x20 in bank 0 and it must also be defined at 0xa 0 in bank 1). the user register, status_temp, must be defined in bank 0. the example 9-3: stores the w register stores the status register in bank 0 executes the isr code restores the status (and bank select bit register) restores the w register example 9-3: saving the status and w registers in ram address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets (1) 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 ?c m i f ? ? ? ? ? ? -0-- ---- -0-- ---- 8ch pie1 ?c m i e ? ? ? ? ? ? -0-- ---- -0-- ---- note 1: other (non power-up) resets include mclr reset, brown-out reset and watchdog timer reset during normal operation. movwf w_temp ;copy w to temp register, ;could be in either bank swapf status,w ;swap status to be saved into w bcf status,rp0 ;change to bank 0 regardless ;of current bank movwf status_temp ;save status to bank 0 ;register : : (isr) : swapf status_temp, w ;swap status_temp register ;into w, sets bank to origi- nal ;state movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w downloaded from: http:///
pic16c62x ds30235j-page 58 ? 2003 microchip technology inc. 9.7 watchdog timer (wdt) the watchdog timer is a free running on-chip rc osci l- lator which does not require any external components . this rc oscillator is separate from the rc oscillato r of the clkin pin. that means that the wdt will run, eve n if the clock on the osc1 and osc2 pins of the devic e has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by programming the configuration bit wdte as clear (section 9.1). 9.7.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out periods vary with tempera - ture, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writi ng to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and pre vent it from timing out and generating a device reset. the to bit in the status register will be cleared upon a watchdog timer time-out. 9.7.2 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time-out occurs. figure 9-17: watchdog timer block diagram table 9-7: summary of watchdog timer registers 0 m u x from tmr0 clock source (figure 6-6) to tmr0 (figure 6-6) postscaler watchdog timer psa 8 - to -1 mux psa wdt time-out 1 0 1 wdt enable bit ps<2:0> note: t0se, t0cs, psa, ps<2:0> are bits in the option regist er. 8 mux address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets 2007h config. bits ? boden cp1 cp0 pwrte wdte fosc1 fosc0 ? ? 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded cells are not used by the watchdog ti mer. note: _ = unimplemented location, read as ?0? + = reserved for future use downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 59 pic16c62x 9.8 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit in the status register is cleared, the to bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they h ad, before sleep was executed (driving high, low, or hi- impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd or v ss with no external circuitry drawing current from the i/o pin and the comparators and v ref should be disabled. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by fl oat- ing inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 9.8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin 2. watchdog timer wake-up (if wdt was enabled) 3. interrupt from rb0/int pin, rb port change, or the peripheral interrupt (comparator). the first event will cause a device reset. the two latter events are considered a continuation of prog ram execution. the to and pd bits in the status register can be used to determine the cause of device reset. pd bit, which is set on power-up, is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the d evice to wake-up through an interrupt event, the correspo nd- ing interrupt enable bit must be set (enabled). wake -up is regardless of the state of the gie bit. if the g ie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. figure 9-18: wake-up from sleep through interrupt note: it should be noted that a reset generated by a wdt time-out does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wake-up from sleep. the sleep instruction is completely executed. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle to s t (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be ther e for rc osc mode. 3: gie = '1' assumed. in this case, after wake-up, the processor jumps to the interrupt routine. if gie = ' 0', execution will continue in-line. 4: clkout is not available in these osc modes, but show n here for timing reference. downloaded from: http:///
pic16c62x ds30235j-page 60 ? 2003 microchip technology inc. 9.9 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 9.10 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations a re not accessible during normal execution, but are readable and writable during program/verify. only th e least significant 4 bits of the id locations are us ed. 9.11 in-circuit serial programming? the pic16c62x microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and th ree other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. th is also allows the most recent firmware or a custom firmware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low, while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/ verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14-bits of program data are then supplied to or from the device, depending i f the command was a load or a read. for complete details of serial programming, please refer to the pic16c6x/7x/9xx programming specification (ds30228). a typical in-circuit serial programming connection is shown in figure 9-19. figure 9-19: typical in-circuit serial programming connection note: microchip does not recommend code protecting windowed devices. external connector signals to normal connections to normal connections pic16c62x v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 61 pic16c62x 10.0 instruction set summary each pic16c62x instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16c62x instruc - tion set summary in table 10-2 lists byte-oriented , bit- oriented, and literal and control operations. table 10-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destinatio n designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the resu lt of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affec ted by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 10-1: opcode field descriptions the instruction set is highly orthogonal and is gro uped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruction cycle, unless a conditional test is tru e or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed a s a nop . one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruct ion execution time is 2 s. table 10-1 lists the instructions recognized by the mpasm? assembler. figure 10-1 shows the three general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 10-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 label label name tos top of stack pc program counter pclat h program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the specified regi s- ter file location [ ] options ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier) note: to maintain upward compatibility with future picmicro ? products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only downloaded from: http:///
pic16c62x ds30235j-page 62 ? 2003 microchip technology inc. table 10-2: pic16c62x instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01110101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfffdfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffffffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0101 01 01 00bb01bb 10bb 11bb bfffbfff bfff bfff ffffffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 1111 10 00 10 11 11 00 11 00 00 11 11 111x1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkkkkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkkkkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of it self ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as inpu t and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 63 pic16c62x 10.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register. words: 1 cycles: 1 example addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (dest) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w= 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (dest) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 downloaded from: http:///
pic16c62x ds30235j-page 64 ? 2003 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '0', then the next instruction is skipped. if bit 'b' is '0', then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two-cycle instruction. words: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_co de before instruction pc = address here after instruction if flag<1> = 0, pc = address true if flag<1>=1, pc = address false downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 65 pic16c62x btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '1', then the next instruction is skipped. if bit 'b' is '1', then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two-cycle instruction. words: 1 cycles: 1(2) example here false true btfss goto flag,1 process_co de before instruction pc = address here after instruction if flag<1> = 0, pc = address false if flag<1> = 1, pc = address true call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. words: 1 cycles: 2 example here call ther e before instruction pc = address here after instruction pc = address there tos = address here+1 clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z= 1 downloaded from: http:///
pic16c62x ds30235j-page 66 ? 2003 microchip technology inc. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z encoding: 00 0001 0000 0011 description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler= 0 to =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (dest) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are complemented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0 x e c decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (dest) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example decf cnt, 1 before instruction cnt = 0x01 z= 0 after instruction cnt = 0x00 z= 1 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 67 pic16c62x decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (dest); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 0, the next instruc- tion, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 0, pc = address here+1 goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. words: 1 cycles: 2 example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (dest) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. words: 1 cycles: 1 example incf cnt, 1 before instruction cnt = 0xff z= 0 after instruction cnt = 0x00 z= 1 downloaded from: http:///
pic16c62x ds30235j-page 68 ? 2003 microchip technology inc. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 0, the next instruc- tion, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=1 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (dest) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z= 1 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register. the don?t cares will assemble as 0?s . words: 1 cycles: 1 example movlw 0x5a after instruction w= 0x5a downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 69 pic16c62x movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0, destination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z= 1 movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to reg- ister 'f'. words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code compatibility with pic16c5x products. since option is a read- able/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibil- ity with future picmicro ? products, do not use this instruction. downloaded from: http:///
pic16c62x ds30235j-page 70 ? 2003 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example table call table;w contains table ;offset value ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w= 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. words: 1 cycles: 2 example return after interrupt pc = tos downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 71 pic16c62x rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w = 1100 1100 c= 1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. words: 1 cycles: 1 example rrf reg1, 0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w = 0111 0011 c= 0 sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. time-out status bit, to is set. watch- dog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 9.8 for more details. words: 1 cycles: 1 example: sleep register f c downloaded from: http:///
pic16c62x ds30235j-page 72 ? 2003 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2?s complement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w= 1 c= ? after instruction w= 1 c = 1; result is positive example 2: before instruction w= 2 c= ? after instruction w= 0 c = 1; result is zero example 3: before instruction w= 3 c= ? after instruction w= 0xff c = 0; result is negative subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2?s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example 1: subwf reg1,1 before instruction reg1= 3 w= 2 c= ? after instruction reg1= 1 w= 2 c = 1; result is positive example 2: before instruction reg1= 2 w= 2 c= ? after instruction reg1= 0 w= 2 c = 1; result is zero example 3: before instruction reg1= 1 w= 2 c= ? after instruction reg1= 0xff w= 2 c = 0; result is negative downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 73 pic16c62x swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w register. if 'd' is 1, the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 f 7 operation: (w) tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x products. since tris registers are readable and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibil- ity with future picmicro ? prod- ucts, do not use this instruction. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg 1 before instruction reg = 0xaf w=0 x b 5 after instruction reg = 0x1a w=0 x b 5 downloaded from: http:///
pic16c62x ds30235j-page 74 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 75 pic16c62x 11.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tool s: integrated development environment - mplab ? ide software assemblers/compilers/linkers -mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? - picdem msc - microid ? -can - powersmart ? -analog 11.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low cost in-circuit debuggers, t o full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexi bility and power. 11.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source l ines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process downloaded from: http:///
pic16c62x ds30235j-page 76 ? 2003 microchip technology inc. 11.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provi de symbol information that is optimized to the mplab ide debugger. 11.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from pre-compiled libraries, usin g directives from a linker script. the mplib object librarian manages the creation and modification of library files of pre-compiled code. w hen a routine from a library is called from a source file , only the modules that contain that routine will be linked in with the application. this allows large libraries t o be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of ma ny smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 11.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standar d ansi c programs into dspic30f assembly language source. the compiler also supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties, and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been validated and conform to the ansi c library standard . the library includes functions for string manipulati on, dynamic memory allocation, data conversion, time- keeping, and math functions (trigonometric, exponen- tial and hyperbolic). the compiler provides symbolic information for high level source debugging with the mplab ide. 11.6 mplab asm30 assembler, linker, and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object fi les and archives to create an executable file. notable feat ures of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 11.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 11.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instructi on level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pi ns. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high speed simulator is designed to debug, analyze and optimize time intensive dsp routines. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 77 pic16c62x 11.9 mplab ice 2000 high performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and sou rce debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allo w the system to be easily reconfigured for emulation of different processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 11.10 mplab ice 4000 high performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for h igh- end picmicro microcontrollers. software control of th e mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory, and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 11.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low cost, run-time development tool, connecting to the host pc via an rs-232 or high spe ed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability b uilt into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash de bug- ging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by settin g breakpoints, single-stepping and watching variables , cpu status and peripheral registers. running at ful l speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 11.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, and program picmicro devices without a pc connection. it can also set code protection in this mode. 11.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. downloaded from: http:///
pic16c62x ds30235j-page 78 ? 2003 microchip technology inc. 11.14 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer, or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional application components. features include an rs-232 interface, a potentiometer for simulated analog input , push button switches and eight leds. 11.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface, an d a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 11.16 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the d em- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperatur e sensor, four leds, and sample pic18f452 and pic16f877 flash microcontrollers. 11.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 11.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8-, 14-, and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low power operation with the supercapacitor circuit, and jumpers allow o n- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro - visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall a dapter or battery, db-9 rs-232 interface, icd connector fo r programming via icsp and development with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h- bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds , four potentiometers, three push buttons and a proto- typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along wi th the user?s guide. 11.19 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a programmed sample is included. the pro mate ii device programmer, or the picstart plus develop- ment programmer, can be used to reprogram the device for user tailored application development. th e picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 79 pic16c62x 11.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/de-multiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 11.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 11.22 pickit tm 1 flash starter kit a complete "development system in a box", the pickit flash starter kit includes a convenient multi-sectio n board for programming, evaluation, and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user's guide (on cd rom), pickit 1 tutorial software and code for vari- ous applications. also included are mplab ? ide (integrated development environment) software, soft- ware and hardware "tips 'n tricks for 8-pin flash pic ? microcontrollers" handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 11.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 11.24 evaluation and programming tools in addition to the picdem series of circuits, microch ip has a line of evaluation kits and demonstration soft ware for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high power ir driver, delta sigma adc, and flow rate sensor check the microchip web page and the latest product line card for the complete list of demonstration and evaluation kits. downloaded from: http:///
pic16c62x ds30235j-page 80 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 81 pic16c62x 12.0 electrical specifications absolute maximum ratings ? ambient temperature under bias ....................... ................................................... ....................... ............. -40 to +125 c storage temperature ................................. ................................................... ........................ .................... -65 to +150 c voltage on any pin with respect to v ss (except v dd and mclr ) .................................................. .....-0.6v to v dd +0.6v voltage on v dd with respect to v ss .................................................. ................................................... ........... 0 to +7.5v voltage on mclr with respect to v ss (note 2) ................................................... ..............................................0 to +14v voltage on ra4 with respect to v ss ................................................... ................................................... .....................8.5v total power dissipation (note 1) ................................................... ................................................... ......................... 1.0w maximum current out of v ss pin ............................................... ................................................... ........................3 00 ma maximum current into v dd pin ............................................... ................................................... ......................... ..250 ma input clamp current, i ik (v i <0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o <0 or v o >v dd ) ................................................................................................................ 20 ma maximum output current sunk by any i/o pin ............ ................................................... ...................... ...................25 ma maximum output current sourced by any i/o pin......... ................................................... .......................................25 ma maximum current sunk by porta and portb.................................... ................................................... ............200 ma maximum current sourced by porta and portb............ ................................................... ...................... .........200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ). 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latchup. thus, a series resistor of 50-100 should be used when applying a "low" level to the mclr pin rather than pulling this pin directly to v ss . ? notice : stresses above those listed under "absolute maximu m ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other cond itions above those indicated in the operation listings of this specifi cation is not implied. exposure to maximum rating condi tions for extended periods may affect device reliability. downloaded from: http:///
pic16c62x ds30235j-page 82 ? 2003 microchip technology inc. figure 12-1: pic16c62x voltage-frequency graph, -40 c t a +125 c figure 12-2: pic16lc62x voltage-frequency graph, -40 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 83 pic16c62x figure 12-3: pic16c62xa voltage-frequency graph, 0 c t a +70 c figure 12-4: pic16c62xa voltage-frequency graph, -40 c t a 0 c, +70 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. downloaded from: http:///
pic16c62x ds30235j-page 84 ? 2003 microchip technology inc. figure 12-5: pic16lc620a/lc621a/lc622a voltage-frequ ency graph, -40 c t a 0 c figure 12-6: pic16lc620a/lc621a/lc622a voltage-frequ ency graph, 0 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. 2.7 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 85 pic16c62x figure 12-7: pic16cr62xa voltage-frequency graph, 0 c t a +70 c figure 12-8: pic16cr62xa voltage-frequency graph, -4 0 c t a 0 c, +70 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. downloaded from: http:///
pic16c62x ds30235j-page 86 ? 2003 microchip technology inc. figure 12-9: pic16lcr62xa voltage-frequency graph, - 40 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (v olts ) 25 2.0 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 87 pic16c62x figure 12-10: pic16c620a/c621a/c622a/cr620a - 40 vol tage-frequency graph, 0 c t a +70 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 41 0 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinati ons of voltage and frequency. 2: the maximum rated speed of the part limits the permissib le combinations of voltage and frequency. please reference the product identification system s ection for the maximum rated speed of the parts. 3: operation between 20 to 40 mhz requires the followin g: v dd between 4.5v. and 5.5v osc1 externally driven osc2 not connected hs mode commercial temperatures devices qualified for 40 mhz operation have -40 desi gnation (ex: pic16c620a-40/p). 40 downloaded from: http:///
pic16c62x ds30235j-page 88 ? 2003 microchip technology inc. 12.1 dc characteristics: pic16c62x-04 (commercial, in dustrial, extended) pic16c62x-20 (commercial, industrial, extended) pic16lc62x-04 (commercial, industrial, extended) pic16c62x standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62x standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended operating voltage v dd range is the pic16c62x range . param. no. sym characteristic min typ? max units conditions d001 v dd supply voltage 3.0 ? 6.0 v see figures 12-1, 12-2, 12-3, 12-4, and 12-5 d001 v dd supply voltage 2.5 ? 6.0 v see figures 12-1, 12-2, 12-3, 12-4, and 12-5 d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section on power-on reset for details d003 v por v dd start voltage to ensure power-on reset ? v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ?? v/ms see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section on power-on reset for details d005 v bor brown-out detect voltage 3.7 4.0 4.3 v boren configuration bit is cleared d005 v bor brown-out detect voltage 3.7 4.0 4.3 v boren configuration bit is cleared d010 i dd supply current (2) ?? ? 1.8 35 9.0 3.3 70 20 ma a ma f osc = 4 mhz, v dd = 5.5v, wdt disabled, xt mode, ( note 4 )* f osc = 32 khz, v dd = 4.0v, wdt disabled, lp mode f osc = 20 mhz, v dd = 5.5v, wdt disabled, hs mode d010 i dd supply current (2) ?? 1.4 26 2.5 53 ma a f osc = 2.0 mhz, v dd = 3.0v, wdt disabled, xt mode, ( note 4 ) f osc = 32 khz, v dd = 3.0v, wdt disabled, lp mode d020 i pd power-down current (3) ? 1.0 2.5 15 a a v dd =4.0v, wdt disabled (125 c) d020 i pd power-down current (3) ? 0.7 2 a v dd =3.0v, wdt disabled * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 89 pic16c62x 12.1 dc characteristics: pic16c62x-04 (commercial, in dustrial, extended) pic16c62x-20 (commercial, industrial, extended) pic16lc62x-04 (commercial, industrial, extended) (c ont.) pic16c62x standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62x standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended operating voltage v dd range is the pic16c62x range . param . no. sym characteristic min typ? max units conditions d022 d022a d023 d023a ? i wdt ? i bor ? i com p ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 350 ?? 20 25 425 100 300 a a a a a v dd =4.0v (125 c) bod enabled, v dd = 5.0v v dd = 4.0v v dd = 4.0v d022 d022a d023 d023a ? i wdt ? i bor ? i com p ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 350 ?? 15 425 100 300 a a a a v dd =3.0v bod enabled, v dd = 5.0v v dd = 3.0v v dd = 3.0v 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. downloaded from: http:///
pic16c62x ds30235j-page 90 ? 2003 microchip technology inc. 12.2 dc characteristics: pic16c62xa-04 (commercial, i ndustrial, extended) pic16c62xa-20 (commercial, industrial, extended) pic16lc62xa-04 (commercial, industrial, extended) pic16c62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions d001 v dd supply voltage 3.0 ? 5.5 v see figures 12-1, 12-2, 12-3, 12-4, and 12-5 d001 v dd supply voltage 2.5 ? 5.5 v see figures 12-1, 12-2, 12-3, 12-4, and 12-5 d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section on power-on reset for details d003 v por v dd start voltage to ensure power-on reset ? v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section on power-on reset for details d005 v bor brown-out detect voltage 3.7 4.0 4.35 v boren configuratio n bit is cleared d005 v bor brown-out detect voltage 3.7 4.0 4.35 v boren configuration bit is cleared * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 91 pic16c62x 12.2 dc characteristics: pic16c62xa-04 (commercial, i ndustrial, extended) pic16c62xa-20 (commercial, industrial, extended) pic16lc62xa-04 (commercial, industrial, extended) ( cont.) pic16c62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions d010 i dd supply current (2, 4) ?? ? ? ? ? 1.2 0.4 1.0 4.0 4.0 35 2.0 1.2 2.0 6.0 7.0 70 ma ma ma ma ma a f osc = 4 mhz, v dd = 5.5v, wdt disabled, xt mode, (note 4)* f osc = 4 mhz, v dd = 3.0v, wdt disabled, xt mode, (note 4)* f osc = 10 mhz, v dd = 3.0v, wdt dis- abled, hs mode, (note 6) f osc = 20 mhz, v dd = 4.5v, wdt dis- abled, hs mode f osc = 20 mhz, v dd = 5.5v, wdt dis- abled*, hs mode f osc = 32 khz, v dd = 3.0v, wdt dis- abled, lp mode d010 i dd supply current (2) ?? ? 1.2 ? 35 2.0 1.1 70 ma ma a f osc = 4 mhz, v dd = 5.5v, wdt disabled, xt mode, (note 4)* f osc = 4 mhz, v dd = 2.5v, wdt disabled, xt mode, (note 4) f osc = 32 khz, v dd = 2.5v, wdt dis- abled, lp mode d020 i pd power-down current (3) ?? ? ? ?? ? ? 2.2 5.0 9.0 15 a a a a v dd = 3.0v v dd = 4.5v* v dd = 5.5v v dd = 5.5v extended temp. d020 i pd power-down current (3) ?? ? ? ?? ? ? 2.0 2.2 9.0 15 a a a a v dd = 2.5v v dd = 3.0v* v dd = 5.5v v dd = 5.5v extended temp. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. downloaded from: http:///
pic16c62x ds30235j-page 92 ? 2003 microchip technology inc. 12.2 dc characteristics: pic16c62xa-04 (commercial, i ndustrial, extended) pic16c62xa-20 (commercial, industrial, extended) pic16lc62xa-04 (commercial, industrial, extended (c ont.) pic16c62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions d022 d022a d023 d023a ? i wdt ? i bor ? i comp ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 75 30 80 10 12 125 60 135 a a a a a v dd = 4.0v (125 c) bod enabled, v dd = 5.0v v dd = 4.0v v dd = 4.0v d022 d022a d023 d023a ? i wdt ? i bor ? i comp ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 75 30 80 10 12 125 60 135 a a a a a v dd =4.0v (125 c) bod enabled, v dd = 5.0v v dd = 4.0v v dd = 4.0v 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 93 pic16c62x 12.3 dc characteristics: pic16cr62xa-04 (commercial, industrial, extended) pic16cr62xa-20 (commercial, industrial, extended) pic16lcr62xa-04 (commercial, industrial, extended) pic16cr62xa-04 pic16cr62xa-20 standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lcr62xa-04 standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions d001 v dd supply voltage 3.0 ? 5.5 v see figures 12-7, 12-8, 12-9 d001 v dd supply voltage 2.5 ? 5.5 v see figures 12-7, 12-8, 12-9 d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section on power-on reset for details d003 v por v dd start voltage to ensure power-on reset ? v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section on power-on reset for details d005 v bor brown-out detect voltage 3.7 4.0 4.35 v boren configuratio n bit is cleared d005 v bor brown-out detect voltage 3.7 4.0 4.35 v boren configuration bit is cleared d010 i dd supply current (2) ?? ? ? ? ? 1.2 500 1.0 4.0 3.0 35 1.7 900 2.0 7.0 6.0 70 ma a ma ma ma a f osc = 4 mhz, v dd = 5.5v, wdt disabled, xt mode, ( note 4 )* f osc = 4 mhz, v dd = 3.0v, wdt disabled, xt mode, ( note 4 ) f osc = 10 mhz, v dd = 3.0v, wdt disabled, hs mode, ( note 6 ) f osc = 20 mhz, v dd = 5.5v, wdt disabled*, hs mode f osc = 20 mhz, v dd = 4.5v, wdt disabled, hs mode f osc = 32 khz, v dd = 3.0v, wdt disabled, lp mode d010 i dd supply current (2) ?? ? 1.2 400 35 1.7 800 70 ma a a f osc = 4.0 mhz, v dd = 5.5v, wdt disabled, xt mode, ( note 4 )* f osc = 4.0 mhz, v dd = 2.5v, wdt disabled, xt mode ( note 4 ) f osc = 32 khz, v dd = 2.5v, wdt disabled, lp mode downloaded from: http:///
pic16c62x ds30235j-page 94 ? 2003 microchip technology inc. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. pic16cr62xa-04 pic16cr62xa-20 standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lcr62xa-04 standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 95 pic16c62x 12.3 dc characteristics: pic16cr62xa-04 (commercial, industrial, extended) pic16cr62xa-20 (commercial, industrial, extended) pic16lcr62xa-04 (commercial, industrial, extended) (cont.) pic16cr62xa-04 pic16cr62xa-20 standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lcr62xa-04 standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions d020 i pd power-down current ( 3 ) ?? ? ? 200 0.400 0.600 5.0 950 1.8 2.2 9.0 na a a a v dd = 3.0v v dd = 4.5v* v dd = 5.5v v dd = 5.5v extended temp. d020 i pd power-down current (3) ?? ? ? 200 200 0.600 5.0 850 950 2.2 9.0 na na a a v dd = 2.5v v dd = 3.0v* v dd = 5.5v v dd = 5.5v extended d022 d022a d023 d023a ? i wdt ? i bor ? i comp ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 75 30 80 10 12 125 60 135 a a a a a v dd =4.0v (125 c) bod enabled, v dd = 5.0v v dd = 4.0v v dd = 4.0v d022 d022a d023 d023a ? i wdt ? i bor ? i comp ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 75 30 80 10 12 125 60 135 a a a a a v dd =4.0v (125 c) bod enabled, v dd = 5.0v v dd = 4.0v v dd = 4.0v 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loadi ng and switching rate, oscillator type, internal code execution pa ttern, and temperature also have an impact on the curre nt consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured wi th the part in sleep mode, with all i/o pins in hi-impe dance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this per ipheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. downloaded from: http:///
pic16c62x ds30235j-page 96 ? 2003 microchip technology inc. 12.4 dc characteristics: pic16c62x/c62xa/cr62xa (commercial, industrial, extended) pic16lc62x/lc62xa/lcr62xa (commercial, industrial, extended) pic16c62x/c62xa/cr62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62x/lc62xa/lcr62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions v il input low voltage i/o ports d030 with ttl buffer v ss ?0 . 8 v 0.15 v dd vv dd = 4.5v to 5.5v otherwise d031 with schmitt trigger input v ss ? 0.2 v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) vss ? 0.2 v dd v (note 1) d033 osc1 (in xt and hs) vss ? 0.3 v dd v osc1 (in lp) vss ? 0.6 v dd - 1.0 v v il input low voltage i/o ports d030 with ttl buffer v ss ? 0.8v 0.15 v dd v v dd = 4.5v to 5.5v otherwise d031 with schmitt trigger input v ss ? 0.2 v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) vss ? 0.2 v dd v (note 1) d033 osc1 (in xt and hs) vss ? 0.3 v dd v osc1 (in lp) vss ? 0.6 v dd - 1.0 v v ih input high voltage i/o ports d040 with ttl buffer 2.0v 0.25 v dd + 0.8v ?v dd v dd vv dd = 4.5v to 5.5v otherwise d041 with schmitt trigger input 0.8 v dd ? v dd d042 mclr ra4/t0cki 0.8 v dd ? v dd v d043 d043a osc1 (xt, hs and lp) osc1 (in rc mode) 0.7 v dd 0.9 v dd ? v dd v (note 1) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmit t trigger input. it is not recommended that the pic16 c62x(a) be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measu red at different input voltages . 3: negative current is defined as coming out of the pin. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 97 pic16c62x 12.4 dc characteristics: pic16c62x/c62xa/cr62xa (commercial, industrial, ext ended) pic16lc62x/lc62xa/lcr62xa (commercial, industrial, extended) (cont.) pic16c62x/c62xa/cr62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62x/lc62xa/lcr62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions v ih input high voltage i/o ports d040 with ttl buffer 2.0v 0.25 v dd + 0.8v ? v dd v dd v v dd = 4.5v to 5.5v otherwise d041 with schmitt trigger input 0.8 v dd ? v dd d042 mclr ra4/t0cki 0.8 v dd ? v dd v d043 d043a osc1 (xt, hs and lp) osc1 (in rc mode) 0.7 v dd 0.9 v dd ? v dd v (note 1) d070 i purb portb weak pull-up current 50 200 400 a v dd = 5.0v, v pin = v ss d070 i purb portb weak pull-up current 50 200 400 a v dd = 5.0v, v pin = v ss i il input leakage current (2, 3) i/o ports (except porta) 1.0 av ss v pin v dd , pin at hi-impedance d060 porta ? ? 0.5 avss v pin v dd , pin at hi-impedance d061 ra4/t0cki ? ? 1.0 avss v pin v dd d063 osc1, mclr ?? 5.0 avss v pin v dd , xt, hs and lp osc configuration i il input leakage current (2, 3) i/o ports (except porta) 1.0 a v ss v pin v dd , pin at hi-impedance d060 porta ? ? 0.5 a vss v pin v dd , pin at hi-impedance d061 ra4/t0cki ? ? 1.0 a vss v pin v dd d063 osc1, mclr ? ? 5.0 a vss v pin v dd , xt, hs and lp osc configuration v ol output low voltage d080 i/o ports ? ? 0.6 vi ol = 8.5 ma, v dd = 4.5v, -40 to +85 c ?? 0.6 vi ol = 7.0 ma, v dd = 4.5v, +125 c d083 osc2/clkout (rc only) ? ? 0.6 vi ol = 1.6 ma, v dd = 4.5v, -40 to +85 c ?? 0.6 vi ol = 1.2 ma, v dd = 4.5v, +125 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmit t trigger input. it is not recommended that the pic16 c62x(a) be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measu red at different input voltages . 3: negative current is defined as coming out of the pin. downloaded from: http:///
pic16c62x ds30235j-page 98 ? 2003 microchip technology inc. 12.4 dc characteristics: pic16c62x/c62xa/cr62xa (commercial, industrial, ext ended) pic16lc62x/lc62xa/lcr62xa (commercial, industrial, extended) (cont.) pic16c62x/c62xa/cr62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended pic16lc62x/lc62xa/lcr62xa standard operating conditions (unless otherwise sta ted) operating temperature -40 c t a +85 c for industrial and 0 c t a +70 c for commercial and -40 c t a +125 c for extended param. no. sym characteristic min typ? max units conditions v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 to +85 c ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, +125 c d083 osc2/clkout (rc only) ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 to +85 c ? ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, +125 c v oh output high voltage (3) d090 i/o ports (except ra4) v dd -0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, +125 c d092 osc2/clkout (rc only) v dd -0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, +125 c v oh output high voltage (3) d090 i/o ports (except ra4) v dd -0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, +125 c d092 osc2/clkout (rc only) v dd -0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, +125 c *d150 v od open-drain high voltage 10* 8.5* v ra4 pin pic16c62x, pic16lc62x ra4 pin pic16c62xa, pic16lc62xa, pic16cr62xa, pic16lcr62xa *d150 v od open-drain high voltage 10* 8.5* v ra4 pin pic16c62x, pic16lc62x ra4 pin pic16c62xa, pic16lc62xa, pic16cr62xa, pic16lcr62xa capacitive loading specs on output pins d100 cosc 2 osc2 pin 15 pf in xt, hs and lp modes when external clock used to drive osc1. d101 c io all i/o pins/osc2 (in rc mode) 50 pf capacitive loading specs on output pins d100 cosc 2 osc2 pin 15 pf in xt, hs and lp modes when external clock used to drive osc1. d101 c io all i/o pins/osc2 (in rc mode) 50 pf * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and ar e not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmit t trigger input. it is not recommended that the pic16 c62x(a) be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measu red at different input voltages . 3: negative current is defined as coming out of the pin. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 99 pic16c62x 12.5 dc characteristics: pic16c620a/c621a/c622a-40 (7) (commercial) pic16cr620a-40 (7) (commercial) dc characteristics standard operating conditions (unless otherwise sta ted) operating temperature 0c ta +70c for commercial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 3.0 ? 5.5 v f osc = dc to 20 mhz d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05 * ? ? v/ms see section on power-on reset for details d005 v bor brown-out detect voltage 3.65 4.0 4.35 v boren configuration bit is cleared d010 i dd supply current (2,4) ?? ? ? ? ? 1.2 0.4 1.0 4.0 4.0 35 2.0 1.2 2.0 6.0 7.0 70 ma ma ma ma ma a f osc = 4 mhz, v dd = 5.5v, wdt disabled, xt o sc mode, (note 4) * f osc = 4 mhz, v dd = 3.0v, wdt disabled, xt o sc mode, (note 4) f osc = 10 mhz, v dd = 3.0v, wdt disabled, hs o sc mode, (note 6) f osc = 20 mhz, v dd = 4.5v, wdt disabled, hs o sc mode f osc = 20 mhz, v dd = 5.5v, wdt disabled*, hs o sc mode f osc = 32 khz, v dd = 3.0v, wdt disabled, lp o sc mode d020 i pd power down current (3) ?? ? ? ?? ? ? 2.2 5.0 9.0 15 a a a a v dd = 3.0v v dd = 4.5v* v dd = 5.5v v dd = 5.5v extended d022 d022a d023 d023a ? i wdt ? i bor ? i comp ? i vref wdt current (5) brown-out reset current (5) comparator current for each comparator (5) v ref current (5) ?? ? ? 6.0 75 30 80 10 12 125 60 135 a a a a a v dd = 4.0v (125 c) bod enabled, v dd = 5.0v v dd = 4.0v v dd = 4.0v ? i ee write ? i ee read ? i ee ? i ee operating current operating current standby current standby current ?? ? ? 3 1 30 100 ma ma a a v cc = 5.5v, scl = 400 khz v cc = 3.0v, ee v dd = v cc v cc = 3.0v, ee v dd = v cc 1a f osc lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 0 0 0 ?? ? ? 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c, unless otherwise stated. these parameters are for design gui dance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating volta ge and frequency. other factors such as i/o pin loading and switc hing rate, oscillator type, internal code execution pattern, and temperat ure also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-sta ted, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the osci llator type. power-down current is measured with the part in s leep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti mated by the formula ir = v dd / 2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. 7: see section 12.1 and section 12.3 for 16c62x and 16cr62x device s for operation between 20 mhz and 40 mhz for valid modified characteristics. downloaded from: http:///
pic16c62x ds30235j-page 100 ? 2003 microchip technology inc. 12.5 dc characteristics: pic16c620a/c621a/c622a-40 (7) (commercial) pic16cr620a-40 (7) (commercial) dc characteristics standard operating conditions (unless otherwise sta ted) operating temperature 0c ta +70c for commercial param no. sym characteristic min typ? max unit conditions v il input low voltage i/o ports d030 with ttl buffer v ss ? 0.8v 0.15v dd v v dd = 4.5v to 5.5v, otherwise d031 with schmitt trigger input v ss 0.2v dd v d032 mclr , ra4/t0cki, osc1 (in rc mode) v ss ? 0.2v dd v (note 1) d033 osc1 (in xt and hs) osc1 (in lp) v ss v ss ?? 0.3v dd 0.6v dd - 1.0 v v v ih input high voltage i/o ports d040 with ttl buffer 2.0v 0.25 v dd + 0.8 ? v dd v dd v v dd = 4.5v to 5.5v, otherwise d041 with schmitt trigger input 0.8 v dd v dd d042 mclr ra4/t0cki 0.8 v dd ? v dd v d043 d043a osc1 (xt, hs and lp) osc1 (in rc mode) 0.7 v dd 0.9 v dd ? v dd v (note 1) d070 i purb portb weak pull-up current 50 200 400 a v dd = 5.0v, v pin = v ss i il input leakage current (2, 3) i/o ports (except porta) 1.0 a v ss v pin v dd , pin at hi-impedance d060 porta ? ? 0.5 a vss v pin v dd , pin at hi-impedance d061 ra4/t0cki ? ? 1.0 a vss v pin v dd d063 osc1, mclr ? ? 5.0 a vss v pin v dd , xt, hs and lp osc con- figuration v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 to +85 c ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, +125 c d083 osc2/clkout (rc only) ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 to +85 c ? ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, +125 c v oh output high voltage (3) d090 i/o ports (except ra4) v dd -0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, +125 c d092 osc2/clkout (rc only) v dd -0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, +125 c *d150 v od open drain high voltage 8.5 v ra4 pin capacitive loading specs on output pins d100 c osc 2 osc2 pin 15 pf in xt, hs and lp modes when external clock used to drive osc1. d101 c io all i/o pins/osc2 (in rc mode) 50 pf * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c, unless otherwise stated. these parameters are for design gui dance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating volta ge and frequency. other factors such as i/o pin loading and swit ching rate, oscillator type, internal code execution pattern, and temperat ure also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-st ated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the osci llator type. power-down current is measured with the part in s leep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti mated by the formula ir = v dd / 2r ext (ma) with r ext in k . 5: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 6: commercial temperature range only. 7: see section 12.1 and section 12.3 for 16c62x and 16cr62x device s for operation between 20 mhz and 40 mhz for valid modified characteristics. downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 101 pic16c62x 12.6 dc characteristics: pic16c620a/c621a/c622a-40 (3) (commercial) pic16cr620a-40 (3) (commercial) 12.7 ac characteristics: pic16c620a/c621a/c622a-40 (2) (commercial) pic16cr620a-40 (2) (commercial) dc characteristics power supply pins standard operating conditions (unless otherwise sta ted) operating temperature 0c ta +70c for commercial characteristic sym min typ (1) max units conditions supply voltage v dd 4.5 ? 5.5 v hs option from 20 - 40 mhz supply current (2) i dd ?? 5.5 7.7 11.5 16 ma ma f osc = 40 mhz, v dd = 4.5v, hs mode f osc = 40 mhz, v dd = 5.5v, hs mode hs oscillator operating frequency f osc 20 ? 40 mhz osc1 pin is externally driven, osc2 pin not connected input low voltage osc1 v il v ss ?0.2v dd v hs mode, osc1 externally driven input high voltage osc1 v ih 0.8v dd ?v dd v hs mode, osc1 externally driven * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characteriza tion results at 25c. this data is for design guidance on ly and is not tested. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, o scillator type, bus rate, internal code execution pattern, and tem perature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt disabled, hs mode with osc2 not connected. 3: for device operation between dc and 20 mhz. see table 1 2-1 and table 12-2. ac characteristics all pins except power supply pins standard operating conditions (unless otherwise sta ted) operating temperature 0c ta +70c for commercial characteristic sym min typ (1) max units conditions external clkin frequency f osc 20 ? 40 mhz hs mode, osc1 externally driven external clkin period t osc 25 ? 50 ns hs mode (40), osc1 externally driven clock in (osc1) low or high time t os l, t os h 6 ? ? ns hs mode, osc1 externally driven clock in (osc1) rise or fall time t os r, t os f ? ? 6.5 ns hs mode, osc1 externally driven osc1 (q1 cycle) to port out valid t os h2 io v ? ? 100 ns ? osc1 (q2 cycle) to port input invalid (i/o in hold time) t os h2 io i 50 ? ? ns ? note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: for device operation between dc and 20 mhz. see table 1 2-1 and table 12-2. downloaded from: http:///
pic16c62x ds30235j-page 102 ? 2003 microchip technology inc. table 12-1: comparator specifications operating conditions: v dd range as described in table 12-1, -40 c transitions from 0000 to 1111 . downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 103 pic16c62x 12.8 timing parameter symbology the timing parameter symbols have been created with on e of the following formats: figure 12-11: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp ck clkout osc osc1 io i/o port t0 t0cki mc mclr uppercase letters and their meanings: s f fall p period hh i g h rr i s e i invalid (hi-impedance) v valid l low z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l = 464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2 downloaded from: http:///
pic16c62x ds30235j-page 104 ? 2003 microchip technology inc. 12.9 timing diagrams and specifications figure 12-12: external clock timing table 12-3: external clock timing requirements parameter no. sym characteristic min typ? max units conditions 1a fosc external clkin frequency (1) dc ? 4 mhz xt and rc osc mode, v dd =5.0v dc ? 20 mhz hs osc mode dc ? 200 khz lp osc mode oscillator frequency (1) dc ? 4 mhz rc osc mode, v dd =5.0v 0.1 ? 4 mhz xt osc mode 1 ? 20 mhz hs osc mode dc ? 200 khz lp osc mode 1 tosc external clkin period (1) 250 ? ? ns xt and rc osc mode 50 ? ? ns hs osc mode 5?? s lp osc mode oscillator period (1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 1,000 ns hs osc mode 5?? s lp osc mode 2t cy instruction cycle time (1) 1.0 f osc /4 dc st cys =f osc /4 3* tosl, to s h external clock in (osc1) high or low time 100* ? ? ns xt oscillator, t osc l/h duty cycle 2* ? ? s lp oscillator, t osc l/h duty cycle 20* ? ? ns hs oscillator, t osc l/h duty cycle 4* tosr, to s f external clock in (osc1) rise or fall time 25* ? ? ns xt oscillator 50* ? ? ns lp oscillator 15* ? ? ns hs oscillator 2: * these parameters are characterized but not tested. 3: ? data in "typ" column is at 5.0v, 25 c unless otherwise stated. these parameters are for desig n guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base perio d. all specified values are based on characterization data for that particular oscillator t ype under standard operating conditions with the device executing code. exceeding these specified limits may result i n an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to ope rate at "min." values with an external clock applied to the osc1 pin. when an external clock input is used, the " max." cycle time limit is "dc" (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 13 3 44 2 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 105 pic16c62x figure 12-13: clkout and i/o timing 22 23 note: all tests must be done with specified capacitance loads (fi gure 12-11) 50 pf on i/o pins and clkout. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value downloaded from: http:///
pic16c62x ds30235j-page 106 ? 2003 microchip technology inc. table 12-4: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* to s h 2 c k l osc1 to clkout (1) ?? 75 ? 200 400 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 11* to s h 2 c k h osc1 to clkout (1) ?? 75 ? 200 400 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 12* tc k r clkout rise time (1) ?? 35 ? 100 200 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 13* tc k f clkout fall time (1) ?? 35 ? 100 200 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 14* tckl2iov clkout to port out valid (1) ? ? 20 ns 15* tiov2ckh port in valid before clkout (1) t osc +200 ns t osc +400 ns ?? ?? ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 16* tckh2ioi port in hold after clkout (1) 0 ? ? ns 17* to s h 2 i o v osc1 (q1 cycle) to port out valid ?? 50 150 300 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 18* to s h 2 i o i osc1 (q2 cycle) to port input invalid (i/o in hold time) 100 200 ?? ?? ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ? ? ns 20* tior port output rise time ?? 10 ? 40 80 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 21* tiof port output fall time ?? 10 ? 40 80 ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 22* tinp rb0/int pin high or low time 25 40 ?? ?? ns ns pic16c62x(a) pic16lc62x(a) pic16cr62xa pic16lcr62xa 23 trbp rb<7:4> change interrupt high or low time t cy ? ? ns * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 107 pic16c62x figure 12-14: reset, watchdog timer, oscillator star t-up timer and power-up timer timing figure 12-15: brown-out reset timing table 12-5: reset, watchdog timer, oscillator start- up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2000 ? ? ns -40 to +85 c 31 twdt watchdog timer time-out period (no prescaler) 7* 18 33* ms v dd = 5.0v, -40 to +85 c 32 tost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33 tpwrt power-up timer period 28* 72 132* ms v dd = 5.0v, -40 to +85 c 34 t ioz i/o hi-impedance from mclr low ? 2.0 s 35 t bor brown-out reset pulse width 100* ? ? s3.7v v dd 4.3v * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c, unless otherwise stated. these parameters are for desig n guidance only and are not tested. v dd mclr internal por pwrt timeout osc timeout internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 v dd bv dd 35 downloaded from: http:///
pic16c62x ds30235j-page 108 ? 2003 microchip technology inc. figure 12-16: timer0 clock timing table 12-6: timer0 clock requirements parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period t cy + 40 * n ? ? ns n = prescale value (1, 2, 4, ..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 c, unless otherwise stated. these parameters are for desig n guidance only and are not tested. 41 42 40 ra4/t0cki tmr0 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 109 pic16c62x 13.0 device characterization information the graphs and tables provided in this section are for design guidance and are not tested. in some grap hs or tables, the data presented is outside specified operating r ange (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the s pecified range. the data presented in this section is a statistical summary of data collected on units from different lot s over a period of time. ?typical? represents the mean of the distributi on, while ?max? or ?min? represents (mean + 3 ) and (mean ? 3 ) respectively, where is standard deviation. figure 13-1: i dd vs. frequency (xt mode, v dd = 5.5v) figure 13-2: pic16c622a i pd vs. v dd (wdt disable) 0.20 1. 00 2.0 0 4.00 frequency (mhz) 1.20 1.00 0.8 0.6 0.4 0.2 0.00 i dd (ma) v dd (v) 3 4 5 6 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 i pd (ua) downloaded from: http:///
pic16c62x ds30235j-page 110 ? 2003 microchip technology inc. figure 13-3: i dd vs. v dd (xt osc 4 mhz) figure 13-4: i o i vs . v ol , v dd = 3.0v) 1.00 v dd (v olts ) i dd (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 2.5 3 3.5 4 4.5 5 5.5 vol (v) 30 25 20 15 10 5 0 i o i (ma) 0 . 5 11 . 522 . 5 3 35 40 45 50 max -40c typ 25c min 85c downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 111 pic16c62x figure 13-5: i oh vs . v oh , v dd = 3.0v) figure 13-6: i o i vs . v ol , v dd = 5.5v) v oh (v) -10 -15 -20 -25 i oh (ma) 0 . 5 11 . 522 . 5 3 -5 0 max -40c typ 25c min 85c vol (v) 60 50 40 30 20 10 0 i o i (ma) 0 . 5 11 . 522 . 5 3 70 80 90 100 max -40c typ 25c min 85c downloaded from: http:///
pic16c62x ds30235j-page 112 ? 2003 microchip technology inc. figure 13-7: i oh vs . v oh , v dd = 5.5v) v oh (v) -20 -30 -40 -50 i oh (ma) 3 3.5 4 4.5 5 5.5 -10 0 max -40c typ 25c min 85c downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 113 pic16c62x 14.0 packaging information 18-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 * controlling parameter significant characteristic jedec equivalent: mo-036 drawing no. c04-010 downloaded from: http:///
pic16c62x ds30235j-page 114 ? 2003 microchip technology inc. 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 115 pic16c62x 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic downloaded from: http:///
pic16c62x ds30235j-page 116 ? 2003 microchip technology inc. 20-lead plastic shrink small outline (ss) ? 209 mi l, 5.30 mm (ssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 117 pic16c62x 14.1 package marking information 20-lead ssop xxxxxxxxxx aabbcde xxxxxxxxxx xxxxxxxx xxxxxxxx aabbcde 18-lead cerdip windowed 18-lead soic (.300") xxxxxxxxxxxx aabbcde xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx aabbcde 18-lead pdip example -04i / 218 9951cbp pic16c622a 16c622 /jw 9901cba example example -04i / s0218 9918cdk pic16c622 pic16c622a -04i / p456 9923cba example legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot b e marked on one line, it will be carried over to the next line thus limiting the n umber of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, a ny special marking adders are included in qtp price. downloaded from: http:///
pic16c62x ds30235j-page 118 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 119 pic16c62x appendix a: enhancements the following are the list of enhancements over the pic16c5x microcontroller family: 1. instruction word length is increased to 14 bits. this allows larger page sizes both in program memory (4k now as opposed to 512 before) and register file (up to 128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. pa2, pa1, pa0 bits are removed from status register. 3. data memory paging is slightly redefined. status register is modified. 4. four new instructions have been added: return , retfie , addlw , and sublw . two instructions tris and option are being phased out, although they are kept for compatibility with pic16c5x. 5. option and tris registers are made addressable. 6. interrupt capability is added. interrupt vector i s at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five differe nt reset (and wake-up) types are recognized. registers are reset differently. 10. wake-up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt-on- change feature. 13. timer0 clock input, t0cki pin is also a port pin (ra4/t0cki) and has a tris bit. 14. fsr is made a full 8-bit register. 15. ?in-circuit programming? is made possible. the user can program pic16cxx devices using only five pins: v dd , v ss , v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power- on-reset (por ) status bit and a brown-out reset status bit (bod ). 17. code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 18. porta inputs are now schmitt trigger inputs. 19. brown-out reset reset has been added. 20. common ram registers f0h-ffh implemented in bank1. appendix b: compatibility to convert code written for pic16c5x to pic16cxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h. downloaded from: http:///
pic16c62x ds30235j-page 120 ? 2003 microchip technology inc. notes: downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 121 pic16c62x index a addlw instruction .................................... ......................... 63 addwf instruction .................................... ......................... 63 andlw instruction .................................... ......................... 63 andwf instruction .................................... ......................... 63 architectural overview ................................. ......................... 9 assembler mpasm assembler...................................... ............... 75 b bcf instruction ...................................... ............................. 64 block diagram timer0............................................. .......................... 31 tmr0/wdt prescaler ................................. ......... 34 brown-out detect (bod) .............................. ...................... 50 bsf instruction ...................................... ............................. 64 btfsc instruction.................................... ........................... 64 btfss instruction .................................... ........................... 65 c c compilers mplab c17 .......................................... ...................... 76 mplab c18 .......................................... ...................... 76 mplab c30 .......................................... ...................... 76 call instruction ..................................... ............................ 65 clocking scheme/instruction cycle ......................... ........... 12 clrf instruction ..................................... ............................ 65 clrw instruction ..................................... ........................... 66 clrwdt instruction ................................... ........................ 66 code protection ..................................... ............................. 60 comf instruction ..................................... ........................... 66 comparator configuration........................... ........................ 38 comparator interrupts .............................. ........................... 41 comparator module .................................. .......................... 37 comparator operation ............................... ......................... 39 comparator reference ................................ ....................... 39 configuration bits................................. ............................... 46 configuring the voltage reference ................... .................. 43 crystal operation .................................... ............................ 47 d data memory organization ............................. .................... 14 dc characteristics .................................... .................. 87, 101 pic16c717/770/771 ............... 88, 89, 90, 91, 96, 97, 98 decf instruction..................................... ............................ 66 decfsz instruction ................................... ......................... 67 demonstration boards picdem 1 ........................................... ........................ 78 picdem 17 .......................................... ....................... 78 picdem 18r pic18c601/801........................... ......... 79 picdem 2 plus ...................................... ..................... 78 picdem 3 pic16c92x ................................. .............. 78 picdem 4 ........................................... ........................ 78 picdem lin pic16c43x ............................... ............ 79 picdem usb pic16c7x5............................... ........... 79 picdem.net internet/ethernet ....................... ............. 78 development support ................................. ........................ 75 e errata ............................................. ....................................... 3 evaluation and programming tools .................... ................ 79 external crystal oscillator circuit ...................... ................. 48 g general purpose register file ........................ .................... 14 goto instruction ..................................... ........................... 67 i i/o ports .......................................... ................................... 25 i/o programming considerations ...................... ................. 30 id locations........................................ ................................ 60 incf instruction..................................... ............................. 67 incfsz instruction ................................... .......................... 68 in-circuit serial programming....................... ...................... 60 indirect addressing, indf and fsr registers ............ ....... 24 instruction flow/pipelining .......................... ........................ 12 instruction set addlw.............................................. ......................... 63 addwf .............................................. ........................ 63 andlw.............................................. ......................... 63 andwf .............................................. ........................ 63 bcf ................................................ ............................ 64 bsf................................................ ............................. 64 btfsc.............................................. .......................... 64 btfss .............................................. .......................... 65 call............................................... ............................ 65 clrf ............................................... ........................... 65 clrw ............................................... .......................... 66 clrwdt ............................................. ....................... 66 comf ............................................... .......................... 66 decf............................................... ........................... 66 decfsz ............................................. ........................ 67 goto ............................................... .......................... 67 incf ............................................... ............................ 67 incfsz............................................. .......................... 68 iorlw.............................................. .......................... 68 iorwf.............................................. .......................... 68 movf ............................................... .......................... 69 movlw .............................................. ........................ 68 movwf.............................................. ........................ 69 nop................................................ ............................ 69 option............................................. ......................... 69 retfie............................................. .......................... 70 retlw .............................................. ......................... 70 return............................................. ........................ 70 rlf................................................ ............................. 71 rrf ................................................ ............................ 71 sleep .............................................. .......................... 71 sublw.............................................. ......................... 72 subwf.............................................. ......................... 72 swapf.............................................. ......................... 73 tris ............................................... ............................ 73 xorlw .............................................. ........................ 73 xorwf .............................................. ........................ 73 instruction set summary .............................. ...................... 61 int interrupt ...................................... ................................. 56 intcon register..................................... ........................... 20 interrupts ......................................... ................................... 55 iorlw instruction .................................... .......................... 68 iorwf instruction .................................... .......................... 68 m movf instruction..................................... ........................... 69 movlw instruction.................................... ......................... 68 movwf instruction .................................... ........................ 69 mplab asm30 assembler, linker, librarian .............. ....... 76 mplab icd 2 in-circuit debugger ..................... ................ 77 mplab ice 2000 high performance universal in-circuit emulator ................................. ............................. 77 mplab ice 4000 high performance universal in-circuit emulator ................................. ............................. 77 mplab integrated development environment software.... 75 mplink object linker/mplib object librarian ........... ....... 76 downloaded from: http:///
pic16c62x ds30235j-page 122 ? 2003 microchip technology inc. n nop instruction...................................... ............................. 69 o one-time-programmable (otp) devices.................. ........... 7 option instruction................................... .......................... 69 option register ..................................... ........................... 19 oscillator configurations ............................ ......................... 47 oscillator start-up timer (ost) ...................... .................... 50 p package marking information ........................... ................ 117 packaging information ................................ ...................... 113 pcl and pclath ..................................... .......................... 23 pcon register ....................................... ............................ 22 pickit 1 flash starter kit .......................... ........................ 79 picstart plus development programmer ................. ...... 77 pie1 register ....................................... ............................... 21 pir1 register....................................... ............................... 21 port rb interrupt .................................. ............................... 56 porta.............................................. .................................. 25 portb.............................................. .................................. 28 power control/status register (pcon) ................. ............. 51 power-down mode (sleep)............................ ................... 59 power-on reset (por) ................................ ...................... 50 power-up timer (pwrt).............................. ....................... 50 prescaler ............................................ ................................. 34 pro mate ii universal device programmer ................ ..... 77 program memory organization .......................... ................. 13 q quick-turnaround-production (qtp) devices ............... ....... 7 r rc oscillator ........................................ ............................... 48 reset............................................... .................................... 49 retfie instruction................................... ........................... 70 retlw instruction .................................... .......................... 70 return instruction................................... ......................... 70 rlf instruction...................................... .............................. 71 rrf instruction ...................................... ............................. 71 s serialized quick-turnaround-production (sqtp) devices ... 7 sleep instruction .................................... ........................... 71 software simulator (mplab sim)..................... .................. 76 software simulator (mplab sim30)................... ................ 76 special features of the cpu.......................... ..................... 45 special function registers ............................ ..................... 17 stack ............................................... .................................... 23 status register...................................... .............................. 18 sublw instruction.................................... .......................... 72 subwf instruction.................................... .......................... 72 swapf instruction.................................... .......................... 73 t timer0 timer0 ............................................. .......................... 31 timer0 (tmr0) interrupt ............................ ............... 31 timer0 (tmr0) module ............................... .............. 31 tmr0 with external clock............................. .............. 33 timer1 switching prescaler assignment.......................... ....... 35 timing diagrams and specifications.................... ............. 104 tmr0 interrupt ..................................... ............................... 56 tris instruction ..................................... ............................. 73 trisa.............................................. .................................... 25 trisb.............................................. .................................... 28 v voltage reference module ............................ ..................... 43 vrcon register ...................................... .......................... 43 w watchdog timer (wdt)................................ ...................... 58 www, on-line support ............................... ........................ 3 x xorlw instruction .................................... ......................... 73 xorwf instruction.................................... ......................... 73 downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 123 pic16c62x on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the inte rnet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a varie ty of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a variety of microchip specific business information is also available, including listings of microchip sale s offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits.the hot li ne numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 092002 downloaded from: http:///
pic16c62x ds30235j-page 124 ? 2003 microchip technology inc. reader response it is our intention to provide you with the best do cumentation possible to ensure successful use of you r microchip prod- uct. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which ou r documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this d ocument. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30235j pic16c62x 1. what are the best features of this document? 2. how does this document meet your hardware and softwar e development needs? 3. do you find the organization of this document easy t o follow? if not, why? 4. what additions to the document do you think would en hance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (wha t and where)? 7. how would you improve this document? downloaded from: http:///
? 2003 microchip technology inc. ds30235j-page 125 pic16c62x product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical require ment of each oscillator type. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences a nd recommended workarounds. to determine if an errata shee t exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data shee t (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx xxx pattern package temperature range device device pic16c62x: v dd range 3.0v to 6.0v pic16c62xt: v dd range 3.0v to 6.0v (tape and reel) pic16c62xa: v dd range 3.0v to 5.5v pic16c62xat: v dd range 3.0v to 5.5v (tape and reel) pic16lc62x: v dd range 2.5v to 6.0v pic16lc62xt: v dd range 2.5v to 6.0v (tape and reel) pic16lc62xa: v dd range 2.5v to 5.5v pic16lc62xat: v dd range 2.5v to 5.5v (tape and reel) pic16cr620a: v dd range 2.5v to 5.5v pic16cr620at: v dd range 2.5v to 5.5v (tape and reel) pic16lcr620a: v dd range 2.0v to 5.5v pic16lcr620at: v dd range 2.0v to 5.5v (tape and reel) frequency range 04 200 khz (lp osc) 04 4 mhz (xt and rc osc) 20 20 mhz (hs osc) temperature range - = 0 c to +70 c i = -40 c to +85 c e = -40c to +125c package p = pdip so = soic (gull wing, 300 mil body) ss = ssop (209 mil) jw* = windowed cerdip pattern 3-digit pattern code for qtp (blank otherwise) examples: a) pic16c621a - 04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301. b) pic16lc622 - 04i/so = industrial temp., soic package, 200 khz, extended v dd limits. -xx frequency range downloaded from: http:///
ds30235j-page 126 ? 2003 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd marketing support division suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-82966626 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india microchip technology inc. india liaison office marketing support division divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan microchip technology (barbados) inc., taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria microchip technology austria gmbh durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy microchip technology srl via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 united kingdom microchip ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 03/25/03 w orldwide s ales and s ervice downloaded from: http:///

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